Method and structure to provide integrated long channel vertical FinFet device

A vertical FinFET device comprising:

• a fin disposed on a semiconductor substrate, the fin having a lower end in contact with a well region disposed within the substrate;
• a first gate stack comprising a first gate dielectric and a first gate conductor disposed over at least one sidewall of the fin, wherein the first gate conductor includes a vertical portion extending over the at least one sidewall of the fin, and a horizontal portion extending laterally over a portion of the well region on at least one side of the fin, and wherein the vertical portion has a first height and the horizontal portion has a second height that is smaller than the first height;
• a channel region between the first gate conductor and the fin and between the main gate conductor and the well region on the at least one side of the fin;
• and
• a lower source/drain region laterally adjacent to the well region on the at least one side of the fin, wherein the portion of the well region underlying the main gate stack is disposed between the lower source/drain region and the well region in contact with the lower end of the fin;
• and
• an upper spacer formed over the first gate stack,
• wherein the device further includes a second gate stack, the second gate stack and the first gate stack disposed over opposing sidewalls of the fin, wherein at least a portion of a lower surface of the upper spacer contacts each of an upper surface of the vertical portion of the first gate conductor, an upper surface of the first gate dielectric, and an upper surface of the second gate stack, and
• wherein the well region is in physical contact with the lower source/drain region and the first gate dielectric.