Forming a protective layer to prevent formation of leakage paths

A method of fabricating a semiconductor device, comprising:

• forming a source/drain in a substrate and a gate structure over the substrate;
• forming a first via over the source/drain;
• forming a first interlayer dielectric (ILD) over the first via and over the gate structure;
• forming a second via over the first via;
• forming a second ILD over the first ILD and over the second via;
• forming a first recess that extends vertically through the second ILD and forming a second recess that extends vertically through the second ILD and the first ILD, wherein the first recess at least partially exposes an upper surface of the second via, and wherein the second recess is aligned with the gate structure;
• forming a first protective layer in the first recess and forming a second protective layer in the second recess;
• performing a first etching process to remove a bottom segment of the first protective layer and a bottom segment of the second protective layer;
• and
• performing a second etching process to vertically extend the second recess until an upper surface of the gate structure is exposed.

A semiconductor device, comprising:

• a source/drain formed in a substrate;
• a gate structure formed over the substrate;
• a first via disposed over and electrically coupled to the source/drain;
• a first interlayer dielectric (ILD) disposed over the first via and over the gate structure;
• a second ILD disposed over the first ILD;
• a second via that extends vertically through the first ILD, wherein the second via is electrically coupled to the first via;
• a third via that extends vertically through the second ILD, wherein the third via is electrically coupled to the second via, wherein a bottom surface of the third via is wider than a top surface of the second via;
• and
• a fourth via that extends vertically through the second ILD and through the first ILD, wherein the fourth via is electrically coupled to the gate structure.