High resistivity SOI wafers and a method of manufacturing thereof

A multilayer structure comprising:

• a single crystal silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal silicon wafer handle substrate and the other of which is a back surface of the single crystal silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer handle substrate, and a central plane of the single crystal silicon wafer handle substrate between the front and back surfaces of the single crystal silicon wafer handle substrate, wherein the single crystal silicon wafer handle substrate comprises a p-type dopant and has a bulk resistivity between about 750 Ohm-cm and about 100,000 Ohm-cm;
• an intermediate semiconductor layer having electron affinity lower than that of the single crystal silicon wafer handle substrate, wherein the intermediate semiconductor layer is between the front surface of the single crystal silicon wafer handle substrate and a charge trapping layer and further wherein the intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprising a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, and any combination thereof wherein x, y, and z are molar ratios with values between 0.1 and 0.9, and further wherein the molar ratio of Ge in the intermediate semiconductor layer increases in the direction perpendicular from the single crystal silicon wafer handle substrate and toward the charge trapping layer;
• the charge trapping layer between the intermediate semiconductor layer and a semiconductor oxide layer;
• the semiconductor oxide layer in interfacial contact with the charge trapping layer;
• and
• a single crystal silicon device layer in interfacial contact with the semiconductor oxide layer.