Semiconductor structure having a group iii-v semiconductor layer comprising a hexagonal mesh crystalline structure

A semiconductor structure comprising:

• a substrate,
• a first semiconductor layer, wherein a material of the substrate and a semiconductor of the first semiconductor layer are crystalline materials having in-plane lattice parameters and the first semiconductor layer is arranged on the substrate such that in-plane lattice parameters of the first semiconductor layer are not the same as in-plane lattice parameters of the material of the substrate,
• first and second stacks each comprising a plurality of second and third layers, wherein the second and third layers are arranged such that within said first and second stack a pair of second layers sandwich at least one third layer and a pair of third layers sandwich at least one second layer and the plurality of second and third layers comprise a semiconductor, the first stack being located between the substrate and the first semiconductor layer, and the second stack being located between the first stack and the first semiconductor layer,
• a fourth semiconductor layer with similar or approximately the same composition as the semiconductor in the first semiconductor layer and located between the first and the second stacks,
• a relaxation layer consisting of AIN and located between the fourth semiconductor layer and the second stack,
• wherein the semiconductors in the first semiconductor layer, the second layers, the third layers, and the fourth semiconductor layer has the formula AlxGayIn(1-x-y)N, where 0<X<1, 0<Y <1 and (X+Y) 1,
• and in each of the first and the second stacks:
• the ratio of Ga in the semiconductor in the second layers varies and increases from one second layer to the next along a direction from the substrate to the first semiconductor layer,
• the ratio of Ga in the semiconductor in the third layers is constant or varies and decreases from one third layer to the next along the direction from the substrate to the first semiconductor layer such that an average in-plane lattice parameter of each group of a second layer and an adjacent third layer increases from one group to the next in the first stack along said direction from the substrate to the first semiconductor layer,
• the thickness of each of the second and third layers is less than about 5 nm, and each second layer is in direct contact with at least one of the third layers
• wherein at least one of the following conditions is met:
• (i) each of the second layers comprises a uniform Ga content or (ii) except for the top most second layer, each second layer is in direct contact with two third layers on opposite sides of each of the second layers, and
• wherein
• the first stack is in physical or direct contact with the fourth semiconductor layer, or
• the second stack is in physical or direct contact with the relaxation layer, or
• the first stack is in physical or direct contact with the fourth semiconductor layer and the second stack is in physical or direct contact with the relaxation layer, or
• the first stack is in direct contact with the fourth semiconductor layer, the fourth semiconductor layer is in direct contact with the relaxation layer, and the relaxation layer is in direct contact with the second stack.