Leakage source detection by scanning access lines

A method, comprising:

• coupling a first subset of access lines of a first set of access lines of a memory die have a first length with a substrate;
• isolating a second subset of access lines of the first set from the substrate, the second subset different than the first subset;
• applying an electron beam to the first set of access lines based at least in part on coupling the first subset with the substrate and isolating the second subset from the substrate;
• scanning, with the electron beam, a second set of access lines of the memory die having a second length different from the first length;
• determining a first error rate associated with the first set of access lines based at least in part on scanning the first set of access lines;
• determining a second error rate associated with the second set of access lines based at least in part on scanning the second set of access lines;
• and
• categorizing a performance of the memory die based at least in part on the first error rate associated with the first set of access lines and the second error rate associated with the second set of access lines.

A method, comprising:

• etching word lines of a plurality of memory tiles of a memory die to a first length, the plurality of memory tiles comprising a first memory tile;
• etching word lines of a second memory tile to a second length shorter than the first length, wherein etching the word lines of the second memory tile comprises isolating one or more portions of each of the word lines from vias of the second memory tile, wherein a remaining portion of the word lines having the second length is coupled with the vias;
• scanning, with an electron beam, the word lines of the first memory tile having the first length and the word lines of the second memory tile having the second length;
• and
• determining a performance of the memory die based at least in part on the scanning the first memory tile and the second memory tile.

A method, further comprising:

• etching word lines of a plurality of memory tiles of a memory die to a first length, the plurality of memory tiles comprising a first memory tile;
• etching word lines of a second memory tile to a second length shorter than the first length;
• scanning with an electron beam, the word lines of the first memory tile having the first length and the word lines of the second memory tile having the second length, wherein scanning the word lines of the first memory tile and the word lines of the second memory tile occurs during manufacturing processes of the memory die;
• and
• determining performance of the memory die based at least in part on the scanning the first memory tile and the second memory tile.