Failing address registers for built-in self tests
AssigneeInternational Business Machines Corporation
InventorsUma Srinivasan, Thomas J. Knips, Gregory J. Fredeman, Matthew Steven Hyde, Thomas E. Miller
Life of this patent
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Abstract
A computer-implemented method includes receiving a memory address of a memory location in a memory that has been identified to be failing. The method further includes determining that the memory location is from a particular portion of the memory. The method further includes, in response to a number of memory locations that are identified to be failing from the particular portion of the memory being below a predetermined threshold, logging the memory address in a set of failing address registers associated with the memory, otherwise, skipping the logging of the memory address in the failing address registers.
Claims17
A computer-implemented method comprising:
- receiving a first memory address that has been identified to be failing, the first memory address located in a first sub-array of a memory;
- receiving a second memory address that has been identified to be failing, the second memory address located in a second sub-array of the memory;
- in response to a number of memory addresses identified to be failing from the first sub-array of the memory being below a predetermined threshold, logging the first memory address in a set of failing address registers associated with the memory;
- and
- in response to a number of memory addresses identified to be failing from the second sub-array of the memory being above the predetermined threshold, preventing the second memory address from being logged in the set of failing address registers.
A system comprising:
- a memory system comprising a plurality of portions;
- and
- a memory controller communicatively coupled with the memory system, the memory controller configured to perform a method comprising:
- receiving a first memory address that has been identified to be failing, the first memory address located in a first sub-array of a memory;
- receiving a second memory address that has been identified to be failing, the second memory address located in a second sub-array of the memory;
- in response to a number of memory addresses identified to be failing from the first sub-array of the memory being below a predetermined threshold, logging the first memory address in a set of failing address registers associated with the memory;
- and
- in response to a number of memory addresses identified to be failing from the second sub-array of the memory being above the predetermined threshold, preventing the second memory address from being logged in the set of failing address registers.
A computer program product computer-readable memory that has computer-executable instructions stored thereupon, the computer-executable instructions when executed by a processor cause the processor to perform a method comprising:
- receiving a first memory address that has been identified to be failing, the first memory address located in a first sub-array of a memory;
- receiving a second memory address that has been identified to be failing, the second memory address located in a second sub-array of the memory;
- in response to a number of memory addresses identified to be failing from the first sub-array of the memory being below a predetermined threshold, logging the first memory address in a set of failing address registers associated with the memory;
- and
- in response to a number of memory addresses identified to be failing from the second sub-array of the memory being above the predetermined threshold, preventing the second memory address from being logged in the set of failing address registers.
Dependencies are inferred from the claim text.