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US 11,081,199 B2Granted
Shift register and method of driving the same, gate driving circuit, display device
AssigneesHefei Xinsheng Optoelectronics Technology Co., Ltd., Boe Technology Group Co., Ltd.
InventorXuehuan Feng
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Abstract
The present application provides a shift register and a method of driving the same, and a gate driving circuit. The shift register includes a detection sub-shift register. The detection sub-shift register includes: a detection input sub-circuit configured to provide a signal of the first input terminal to the pull-up control node under the control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under the control of the pull-up control node; and a detection output sub-circuit configured to provide a signal of the third clock signal terminal to the first output terminal under the control of the first pull-up node.
Claims20
A shift register, comprising:
- a display sub-shift register;
- and
- a detection sub-shift register coupled to the display sub-shift register, the detection sub-shift register comprising:
- a first input terminal, a first output terminal, a first reset terminal, and a second reset terminal;
- a detection input sub-circuit coupled to a first clock signal terminal, a second clock signal terminal, the first input terminal, a pull-up control node and a first pull-up node of the detection sub-shift register, and configured to provide a signal of the first input terminal to the pull-up control node under control of the first clock signal terminal, and provide a signal of the second clock signal terminal to the first pull-up node under control of the pull-up control node;
- a detection output sub-circuit coupled to the first pull-up node, a third clock signal terminal and the first output terminal, and configured to provide a signal of the third clock signal terminal to the first output terminal under control of the first pull-up node;
- a detection output control sub-circuit coupled to the first output terminal, a first pull-down node and a low-level voltage terminal, and configured to provide a signal of the low-level voltage terminal having a constant low level to the first output terminal under control of the first pull-down node;
- a detection reset sub-circuit coupled to the first reset terminal, the second reset terminal, the first pull-up node, the pull-up control node and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-up node under control of the first reset terminal, and provide the signal of the low-level voltage terminal to the pull-up control node under control of the second reset terminal;
- and
- a detection node control sub-circuit coupled to a first control terminal, a second control terminal, the first pull-up node, the first pull-down node, and the low-level voltage terminal, and configured to provide the signal of the low-level voltage terminal to the first pull-down node under control of the first control terminal, the second control terminal, and the first pull-up node.
7 more elements
A method of driving a shift register,
- the shift register comprising a display sub-shift register and a detection sub-shift register coupled to the display sub-shift register,
- the method comprising:
- in a first stage, providing a signal of a second clock signal terminal having an on level to a first pull-up node of the detection sub-shift register, and providing a signal of a low-level voltage terminal to a first output terminal of the detection sub-shift register;
- in a second stage, providing a signal of the second clock signal terminal having an off level to the first pull-up node of the detection sub-shift register, and providing the signal of the low-level voltage terminal to the first output terminal of the detection sub-shift register;
- in a third stage, providing a signal of the second clock signal terminal having an on level to the first pull-up node of the detection sub-shift register, and providing a signal of a third clock signal terminal having an on level to the first output terminal of the detection sub-shift register;
- in a fourth stage, providing the signal of the low-level voltage terminal to the first pull-up node and the first output terminal of the detection sub-shift register;
- and
- in a fifth stage, making the first pull-up node of the detection sub-shift register remain a level in the fourth stage, and providing the signal of the low-level voltage terminal to the first output terminal of the detection sub-shift register,
- wherein a time period in which the signal of the first pull-up node is at the on level at least partially overlaps with a time period in which the signal of the first output terminal is at the on level, and when the signal of the first pull-up node is at the off level, the signal of the first output terminal is at the off level.
6 more elements
Dependencies are inferred from the claim text.