Suppression of program disturb with bit line and select gate voltage regulation

A semiconductor apparatus, comprising:

• a processing device;
• and
• a non-volatile memory (NVM) device coupled to the processing device, including:
• a memory array comprising NVM cells arranged in rows and columns, wherein each source line of a plurality of source lines and each select-gate (SG) line of a plurality of SG lines respectively couple at least two NVM cells of a same row, and wherein each bit line of a plurality of bit lines couples at least two NVM cells of a same column;
• and
• control circuitry operable to regulate, independently of a power supply voltage, a first voltage of a selected SG line and a second voltage of an unselected bit line, wherein the second voltage is operated to be higher than the power supply voltage, and wherein the control circuitry is further operable to adjust at least one of the first and second voltages responding to a sensing signal.