Inverter based delay chain for calibrating data signal to a clock
AssigneeSanDisk Technologies LLC
InventorTianyu Tang
Life of this patent
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Abstract
Technology is disclosed herein for correcting skew between data signals and a clock signal. In one aspect, a memory system has a delay circuit having delay blocks, with each delay block having one or more inverters. The delay circuit is configured to pass a data signal through either an odd number of the inverters or an even number of the inverters to produce a delayed data signal. The memory system has a skew correction circuit configured to control the number of inverters in the delay circuit through which the data signal is passed in order to correct skew between the data signal and the clock signal. The memory system has a polarity correction circuit configured to invert the data signal in the event that the delay circuit passed the data signal through the odd number of the inverters.
Claims20
An apparatus comprising:
- an interface configured to receive a data signal and a clock signal;
- one or more control circuits in communication with the interface, wherein the one or more control circuits are configured to:
- delay the data signal by a selectable delay to produce a delayed data signal, wherein delaying the data signal inverts the data signal for a first set of the selectable delays and does not invert the data signal for a second set of the selectable delays;
- sample the delayed data signal in response to a transition of the clock signal and produce a sampled data signal;
- scan through different values of the selectable delay in order to calibrate the data signal to the clock signal;
- and
- invert the sampled data signal if the data signal was inverted when delaying the data signal prior to sampling the delayed data signal.
A method comprising:
- receiving a data signal at a first input contact of a memory system;
- receiving a clock signal at a second input contact of the memory system;
- delaying the data signal by different delay times to produce a delayed data signal, including passing the data signal through an odd number of inverters for a first set of the different delay times and passing the data signal through an even number of inverters for a second set of the different delay times;
- sampling the delayed data signal in response to a transition of the clock signal to produce a sampled data signal;
- inverting the sampled data signal in response to the data signal being delayed by any of the first set of the different delay times to produce a comparison data signal;
- using the sampled data signal for the comparison data signal in response to the data signal being delayed by any of the second set of the different delay times;
- and
- correcting skew between the data signal and the clock signal based on an analysis of the comparison data signal that corresponds to delaying the data signal by the first set and the second set of the different delay times.
A non-volatile memory system, comprising:
- a data input contact;
- a clock input contact;
- a delay circuit comprising a plurality of delay blocks each having one or more inverters, wherein the delay circuit is configured to pass a data signal from the data input contact through either an odd number of the inverters or an even number of the inverters to produce a delayed data signal;
- a sampling circuit configured to sample the delayed data signal from the delay circuit based on a clock signal from the clock input contact;
- a skew correction circuit configured to control the number of the inverters in the delay circuit through which the data signal is passed in order to correct skew between the clock signal and the data signal, wherein the skew correction circuit is further configured to store a calibration code based on correcting the skew;
- and
- a polarity correction circuit configured to invert the data signal from the sampling circuit if that the delay circuit passed the data signal through the odd number of the inverters.
Dependencies are inferred from the claim text.