Memory plane structure for ultra-low read latency applications in non-volatile memories

A memory device, comprising:

• a semiconductor substrate in which a memory cell region and a peripheral region are defined, the memory cell region comprising a plurality of co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate, wherein each memory cell plane is comprised of:
• an (m)-number of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate, wherein each sub-plane comprises an (n)-bit programmable memory cell array having an (n)-number of bit lines;
• an (m+1) number of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that, adjacent to each sub-plane is a sense amplifier region wherein, apart from the sense amplifier regions positioned at terminating ends of the memory cell plane, each sense amplifier region is operable with respect to at least a fraction of the (n)-number of bit lines of the two sub-planes immediately adjacent to the sense amplifier region;
• and
• wherein each bit line only traverses one sub-plane and one sense amplifier region.

A method for reducing the bit line capacitance in a non-volatile memory device, comprising:

• in a memory device having a semiconductor substrate in which a memory cell region and a peripheral region are defined, partitioning the memory cell region into a plurality of co-planar memory cell planes arranged in a plane parallel to the semiconductor substrate;
• partitioning each memory cell plane into a plurality of sub-planes disposed adjacent one another along an axis parallel to the semiconductor substrate, wherein each sub-plane comprises an (n)-bit programmable memory cell array having an (n)-number of bit lines;
• and
• arranging a plurality of sense amplifier regions along the axis in an alternating pattern with the plurality of sub-planes such that, adjacent to each sub-plane is a sense amplifier region wherein, apart from the sense amplifier regions positioned at terminating ends of the memory cell plane, each sense amplifier region is operable with respect to at least a fraction of the (n)-number of bit lines of the two sub-planes immediately adjacent to the sense amplifier region;
• and
• wherein each bit line only traverses one sub-plane and one sense amplifier region.