Reverse sensing for data recovery in non-volatile memory structures
AssigneeSanDiskTechnologies LLC
InventorsAbhinav Anand, Young Pil Kim, Dana Lee
Life of this patent
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Abstract
A method for data recovery in a memory array of a non-volatile memory system, wherein the method comprises detecting an electrical short between a word line (WL) of a memory cell transistor and a local source line (LI) of a memory structure of the array, increasing an initial voltage bias at the local source line to a second voltage bias that exceeds a threshold voltage of the shorted memory cell transistor and a voltage level of a bit line of the memory structure, thereby causing a sensing current to flow in a direction from the local source line to the bit line, and sensing at a sense amplifier of the memory structure the sensing current.
Claims20
A method for data recovery in a memory array of a non-volatile memory system, comprising:
- detecting an electrical short between a word line (WL) of a memory cell transistor and a local source line (LI) of a memory structure of the memory array;
- increasing an initial voltage bias at the local source line to a second voltage bias exceeding a threshold voltage of the shorted memory cell transistor and a voltage level of a bit line of the memory structure, thereby causing a sensing current to flow in a direction from the local source line to the bit line;
- and
- sensing at a sense amplifier of the memory structure the sensing current.
A memory controller of a non-volatile memory system, comprising:
- a first communication pathway coupled to a memory array;
- a logic circuit operable to detect an electrical short between a word line (WL) of a memory cell transistor and a local source line (LI) of a memory structure of the memory array;
- and
- the memory controller configured to:
- increase an initial voltage bias at the local source line to a second voltage bias that exceeds a threshold voltage of the shorted memory cell transistor and a voltage level of a bit line of the memory structure, thereby causing a sensing current to flow in a direction from the local source line to the bit line;
- and
- sense at a sense amplifier of the memory structure the sensing current.
A non-volatile storage system, configured to recover data therein that is rendered unreadable due to a word line short, comprising:
- a programmable memory array storing data in a plurality of memory cells addressable by a plurality of word lines;
- and
- a controller communicating with the memory array over a first communication pathway and controlling a logic circuit of the controller to:
- detect an electrical short between a word line (WL) of a memory cell transistor and a local source line (LI) of a memory structure of the memory array;
- increase an initial voltage bias at the local source line to a second voltage bias exceeding a threshold voltage of the shorted memory cell transistor and a voltage level of a bit line of the memory structure, thereby causing a sensing current to flow in a direction from the local source line to the bit line;
- and
- sense at a sense amplifier of the memory structure the sensing current.
Dependencies are inferred from the claim text.