Charge loss compensation
AssigneeMicron Technology, Inc.
InventorsKalyan Chakravarthy C. Kavalipurapu, Jung Sheng Hoei
Life of this patent
Estimating the term…
Abstract
Disclosed in some examples are methods, systems, devices, and machine-readable mediums for compensating for charge loss effects. In some examples, a charge loss may be estimated by a charge loss monitor for a particular unit of a NAND device and may be utilized to select a charge loss compensation scheme. The charge loss may be estimated by the charge loss estimation process by determining a reference read voltage and calculating a bit count resulting from a read at that reference read voltage. The number of bits returned may be used to select the particular charge loss compensation scheme.
Claims17
A memory system comprising:
- a memory array comprising non-volatile memory cells;
- a memory controller comprising one or more hardware processors, the memory controller configured to perform operations comprising:
- applying a first read voltage to a first page of the memory array;
- determining a number of bits read in the first page as a result of the application of the first read voltage;
- estimating a charge loss of a second page based upon the number of bits and a proximity between the first and second pages;
- receiving a read command to read the second page of the memory array;
- determining whether a charge loss compensation is to be applied for the read command;
- responsive to determining that the charge loss compensation is to be applied to the read command, setting a read parameter based upon the estimated charge loss of the second page;
- and
- reading the second page using the read parameter and a second read voltage, the second read voltage different than a reference read level voltage.
A method performed by a controller of a memory system, the method comprising:
- applying a first read voltage to a first page of a memory array of the memory system;
- determining a number of bits read in the first page as a result of the application of the first read voltage;
- estimating a charge loss of a second page based upon the number of bits and a proximity between the first and second pages;
- receiving a read command to read the second page of the memory array;
- determining whether a charge loss compensation is to be applied for the read command;
- responsive to determining that the charge loss compensation is to be applied to the read command, setting a read parameter based upon the estimated charge loss of the second page;
- and
- reading the second page using the read parameter and a second read voltage, the second read voltage different than a reference read level voltage.
A non-transitory machine-readable medium, storing instructions, which when executed by a processor of a memory system, causes the processor to perform operations comprising:
- applying a first read voltage to a first page of a memory array of the memory system;
- determining a number of bits read in the first page as a result of the application of the first read voltage;
- estimating a charge loss of a second page based upon the number of bits and a proximity between the first and second pages;
- receiving a read command to read the second page of the memory array;
- determining whether a charge loss compensation is to be applied for the read command;
- responsive to determining that the charge loss compensation is to be applied to the read command, setting a read parameter based upon the estimated charge loss of the second page;
- and
- reading the second page using the read parameter and a second read voltage, the second read voltage different than a reference read level voltage.
Dependencies are inferred from the claim text.