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US 11,081,185 B2Granted
Non-volatile memory array driven from both sides for performance improvement
AssigneeSanDisk Technologies LLC
InventorsHardwell Chibvongodze, Masatoshi Nishikawa
Life of this patent
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Abstract
A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.
Claims20
A memory apparatus comprising:
- a first set of word lines, each word line of the first set of word lines extending from a first end to a second end to couple a respective row of storage cells of the memory apparatus;
- a second set of word lines, each word line of the second set of word lines extending from a first end to a second end to couple a respective row of storage cells of the memory apparatus, each word line of the second set corresponds to a word line of the first set;
- and
- a connection circuit configured to couple the first end of each word line of the first set of word lines to the first end of a corresponding word line of the second set of word lines and couple the second end of each word line of the first set of word lines to the second end of a corresponding word line of the second set of word lines.
1 more element
An apparatus comprising:
- a three-dimensional array of NAND strings coupled to word lines, the three- dimensional array comprising a selected erase block and an unselected erase block with a trench between the selected erase block and the unselected erase block;
- a word line interconnect configured to electrically couple each word line of the selected erase block to a corresponding word line of the unselected erase block, the corresponding word line positioned in a common layer of the three-dimensional array, the word line interconnect including an external conductive link that couples a selected word line of the selected erase block to an unselected word line of the unselected erase block outside of the three-dimensional array;
- a connection circuit configured to selectively couple one or more of the word lines of the selected erase block and one or more of the word lines of the unselected erase block to a common driver;
- and
- a die controller configured to bias the NAND strings within the selected erase block and bias NAND strings within the unselected erase block in order to execute a storage operation on storage cells of the selected erase block and mitigate effects of the storage operation on storage cells of the unselected erase block.
2 more elements
A method comprising:
- turning drain select gates of NAND strings off to float the NAND strings;
- applying a read voltage to a selected word line of a selected erase block from both ends of the selected word line, the read voltage applied concurrently to a corresponding word line of the unselected erase block from both ends of the corresponding word line by way of a word line interconnect;
- applying a pass voltage to unselected word lines of the selected erase block from both ends of the unselected word lines, the pass voltage applied concurrently to unselected word lines of the unselected erase block from both ends by way of a word line interconnect;
- and
- sensing a read state for storage cells on the selected word line, wherein the floating NAND strings mitigates resistive-capacitive delay on the selected word line and unselected word lines.
2 more elements
Dependencies are inferred from the claim text.