Integrated circuit and computing method thereof

A computing method of an integrated circuit, wherein the integrated circuit comprises a memory array, a plurality of word lines, a plurality of bit lines and a page buffer, the memory array comprises a plurality of memory cells, each formed by a flash transistor, the plurality of word lines respectively connect a row of the plurality of memory cells, the plurality of bit lines are respectively connected with a column of the plurality of memory cells that are connected in series, the page buffer is coupled to the memory array, and the computing method of the integrated circuit comprise:

• performing at least one programming operations, to write weights into the plurality of memory cells, wherein each of the plurality of memory cells is independently written with one of the weights;
• applying input voltages to more than one of the plurality of bit lines in a block of the memory array or to more than one of the plurality of word lines in multiple blocks of the memory array, wherein the memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages;
• and
• summing up the products of the weights and the input voltages by the page buffer or through one of the plurality of bit lines.