Memory device with bit lines disconnected from NAND strings for fast programming

An apparatus, comprising:

• a first block of memory cells, the first block comprising a first stack of alternating conductive and dielectric layers formed on a substrate, the conductive layers are connected to the memory cells, the memory cells are arranged in a first set of NAND strings extending vertically upward from the substrate to a top of the first stack, and the first set of NAND strings comprises rows of data-storing NAND strings interleaved with rows of dummy NAND strings;
• an insulation layer at the top of the first stack;
• a first set of bit lines interleaved with a second set of bit lines above the insulation layer;
• and
• a respective conductive via in the insulation layer for each NAND string of the rows of data-storing NAND strings, a bottom of each respective conductive via contacts a top of each respective NAND string of the rows of data-storing NAND strings, a top of each respective conductive via contacts a respective bit line of the first set of bit lines to electrically connect the first set of bit lines to the data-storing NAND strings, and a bottom of the insulation layer contacts a top of each respective dummy NAND string to electrically disconnect the second set of bit lines from the dummy NAND strings.