Semiconductor device and memory device

A memory device comprising:

• first signal lines that transmit first signals;
• second signal lines that receive the first signals;
• a memory cell array including a memory cell, the memory cell array coupled to one of the first signal lines and the second signal lines;
• and
• a first circuit including a first selector circuit, a second selector circuit, third signal lines, and fourth signal lines, the first selector circuit being coupled to the first signal lines, the second selector circuit being coupled to the second signal lines, the third signal lines being coupled between the first and second selector circuits, and the fourth signal lines being coupled between the first and second selector circuits, wherein
• each of the third signal lines stores a corresponding one of the second signals, and
• each of the fourth signal lines stores a corresponding one of the third signals,
• the first circuit is configured to:
• count a first number of second signals equivalent to corresponding first signal of the first signals, with respect to the first and third signal lines,
• count a second number of third signals equivalent to the corresponding first signal, with respect to the first and fourth signal lines, and
• electrically couple either the third signal lines or the fourth signal lines to the first and second signal lines via the first and second selector circuits, based on a result of comparison between the first number and the second number.