Set/reset methods for crystallization improvement in phase change memories

A method, comprising:

• performing a SET operation on a set of phase change memory cells;
• determining a number of SET/RESET cycles that have been applied to the set of phase change memory cells;
• detecting that a two-step RESET operation should be applied to the set of phase change memory cells in response to detecting that the number of SET/RESET cycles that have been applied to the set of phase change memory cells is greater than a threshold number of cycles;
• determining a first slope for a falling edge of the two-step RESET operation based on the number of SET/RESET cycles that have been applied to the set of phase change memory cells;
• and
• performing the two-step RESET operation with the first slope for the falling edge to the set of phase change memory cells.

An apparatus, comprising:

• one or more control circuits configured to be connected to one or more phase change memory cells, the one or more control circuits are configured to determine a first number of SET/RESET cycles that have been applied to the one or more phase change memory cells and determine a first slope for a falling edge of a first RESET pulse based on the first number of SET/RESET cycles, the one or more control circuits are configured to detect that the first number of SET/RESET cycles that have been applied to the one or more phase change memory cells is greater than a first threshold number of cycles and apply the first RESET pulse with the first slope for the falling edge of the first RESET pulse to the one or more phase change memory cells in response to detection that the first number of SET/RESET cycles that have been applied to the one or more phase change memory cells is greater than the first threshold number of cycles, the one or more control circuits are configured to determine a second number of SET/RESET cycles that have been applied to the one or more phase change memory cells and determine a second slope different from the first slope for a falling edge of a second RESET pulse based on the second number of SET/RESET cycles, the one or more control circuits are configured to apply the second RESET pulse with the second slope for the falling edge of the second RESET pulse to the one or more phase change memory cells.