On-chip security key with phase change memory
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Carl Radens, Ruilong Xie, Juntao Li
Life of this patent
Estimating the term…
Abstract
A method is presented for forming an on-chip security key. The method includes electrically connecting a pair of phase change memory (PCM) elements in series, electrically connecting a programming transistor to the pair of PCM elements, electrically connecting an input of an inverter to a common node of the pair of PCM elements, setting the PCM elements to a low resistance state (LRS) in an initialization stage, applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS), and generating a logic “1” or “0” at the output of the inverter.
Claims20
A method for forming an on-chip security key, the method comprising:
- electrically connecting a pair of phase change memory (PCM) elements in series;
- electrically connecting a programming transistor to the pair of PCM elements;
- electrically connecting an input of an inverter to a common node of the pair of PCM elements;
- setting the PCM elements to a low resistance state (LRS) in an initialization stage;
- applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS);
- and
- generating a logic “1” or “0” at the output of the inverter.
A method for forming an on-chip security key, the method comprising:
- setting a pair of phase change memory (PCM) elements to a low resistance state (LRS) by using a wordline (WL) and a bitline (BL);
- increasing WL voltage to increase current flow through the pair of PCM elements;
- changing one PCM element to a high resistance state (HRS), thus resulting in abrupt decrease of current flow through the PCM elements;
- generating a logic “1” or “0” at an output of an inverter connected to a common node of the pair of PCM elements based on which PCM element changes to HRS first;
- and
- performing a SET operation to erase information.
An on-chip security key generator comprising:
- a pair of phase change memory (PCM) elements electrically connected in series;
- a programming transistor electrically connected to the pair of PCM elements;
- an input of an inverter electrically connected to a common node of the pair of PCM elements;
- and
- an initialization stage for:
- setting the PCM elements to a low resistance state (LRS);
- applying a RESET pulse to generate a security bit and to cause one of the PCM elements to change to a high resistance state (HRS);
- and
- generating a logic “1” or “0” at the output of the inverter.
Dependencies are inferred from the claim text.