US 11,081,167 B1 · Sense amplifier architecture for low supply voltage operations

Abstract

Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.

Claims18

Dependent claims

An apparatus, comprising:

a read circuit configured to read data from a memory cell;
a data latch circuit in communication with the read circuit, the data latch circuit includes a transistor in a non-conducting state, the data latch circuit configured to latch the data from the read circuit and increase a threshold voltage of the transistor after the data is latched;
and
a control circuit configured to determine a chip temperature and apply a first voltage to a source of the transistor to increase the threshold voltage of the transistor after the data is latched based on the chip temperature.

1 more element

Dependencies are inferred from the claim text.

Sense amplifier architecture for low supply voltage operations

Life of this patent

Sense amplifier architecture for low supply voltage operations

Life of this patent

Abstract

Claims18