Non-volatile memory device and control method

A non-volatile memory device, comprising:

• a memory array comprising a plurality of memory strings, each memory string comprising a select gate transistor and a plurality of memory cells connected in series with the select gate transistor;
• a bit line connected to a first memory string of the plurality of memory strings;
• a select gate line connected to the select gate transistor of the first memory string of the plurality of memory strings;
• a plurality of word lines connected to the plurality of memory cells of the first memory string of the plurality of memory strings, each word line connected to a respective memory cell of the first memory string;
• a first control circuit configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period;
• and
• a second control circuit configured to apply a word line signal to a selected word line of the plurality of word lines and apply a plurality of word line pre-pulse signals to word lines disposed between the select gate line and the selected word line during the pre-charge period, wherein voltage levels of the plurality of word line pre-pulse signals are incremental;
• wherein the second control circuit is configured to apply a first word line pre-pulse signal of the plurality of word line pre-pulse signal to a first group of the plurality of word lines disposed adjacent to the selected word line and disposed between the selected word line and the select gate line during the pre-charge period, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signal to a second group of the plurality of word lines disposed adjacent to the first group of the plurality of word lines and disposed between the first group of the plurality of word line and the select gate line during the pre-charge period, and apply a third word line pre-pulse signal of the plurality of word line pre-pulse signal to a third second group of the plurality of word lines disposed adjacent to the second group of the plurality of word lines and between the second group of the plurality of word lines and the select gate line during the pre-charge period, wherein a voltage level of the second word line pre-pulse signal is greater than a voltage level of the first word line pre-pulse signal and a voltage level of the third word line pre-pulse signal is greater than the voltage level of the second word line pre-pulse signal.