Source side precharge and boosting improvement for reverse order program

An apparatus comprising:

• a three-dimensional memory array of NAND strings, each NAND string coupled to a bit line;
• a plurality of drain control lines connected to a drain side of each NAND string;
• a plurality of source control lines connected to a source side of each NAND string;
• a plurality of word lines comprising memory cells and positioned between the plurality of drain control lines and the plurality of source control lines;
• a plurality of drain side dummy word lines coupled to each NAND string between the drain control lines and the word lines;
• a plurality of source side dummy word lines coupled to each NAND string between the source control lines and the word lines;
• a source line coupled to the source side of each NAND string;
• and
• a die controller connected to the plurality of source control lines and the plurality of source side dummy word lines, the die controller to delay discharge of one or more of the source control lines and the source side dummy word lines until after discharge of other ones of the source control lines and the source side dummy word lines during a precharge stage of a program operation, the one or more of the source control lines and the source side dummy word lines selected according to threshold voltage.

A method for retaining a bias in a channel of a NAND string during source-side precharge, comprising:

• activating each of a plurality of source-side select gates coupled to a NAND string between a source line and a plurality of source side dummy word line select gates by biasing the plurality of source-side select gates, the plurality of source side dummy word line select gates adjacent to a memory cell of the NAND string that is coupled to a word line;
• activating each of the plurality of source side dummy word line select gates by biasing the plurality of source side dummy word line select gates;
• biasing a channel of the NAND string by biasing the source line coupled to the NAND string by way of the plurality of source-side select gates;
• and
• discharging the plurality of source-side select gates and the plurality of source side dummy word line select gates such that a first source-side select gate having a first threshold voltage is discharged prior to a second source-side select gate having a second threshold voltage that is higher than the first threshold voltage.