Memory cell arrangement and methods thereof
AssigneeFerroelectric Memory GmbH
InventorsRolf Jähne, Marko Noack
Life of this patent
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Abstract
A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.
Claims18
A memory cell arrangement, comprising:
- a memory cell comprising a first terminal, a second terminal, and a third terminal;
- the memory cell being configured to allow for a control of a current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell, wherein the memory cell comprises a remanently-polarizable layer and is writable into one of at least two memory states, wherein a first memory state of the at least two memory states has a first threshold voltage associated therewith and wherein a second memory state of the at least two memory states has a second threshold voltage associated therewith, wherein the first threshold voltage is different from the second threshold voltage;
- a bitline connected to the first terminal of the memory cell;
- and
- a read-out circuit configured to carry out a read-out operation to read out the memory state of the memory cell, the read-out operation comprising:
- generating a characteristic voltage at the bitline by applying the third voltage at the third terminal of the memory cell and a second voltage at the second terminal of the memory cell, wherein the characteristic voltage is a function of the first threshold voltage and the second threshold voltage and represents the memory state of the memory cell, wherein generating the characteristic voltage at the bitline comprises dynamically charging or discharging the bitline through the memory cell, and
- sensing the characteristic voltage to determine the memory state of the memory cell.
A memory cell arrangement, comprising:
- a memory cell comprising a first terminal, a second terminal, and a third terminal, wherein the memory cell comprises a remanently-polarizable layer and is writable into one of at least two memory states, wherein a first memory state of the at least two memory states has a first threshold voltage associated therewith and wherein a second memory state of the at least two memory states has a second threshold voltage associated therewith, wherein the first threshold voltage is different from the second threshold voltage;
- a bitline connected to the first terminal of the memory cell;
- and
- the memory cell being configured to allow a generation of a characteristic voltage at the bitline by applying a third voltage at the third terminal of the memory cell and a second voltage at the second terminal of the memory cell, wherein the characteristic voltage is a function of the first threshold voltage and the second threshold voltage and represents a memory state of the memory cell;
- wherein the generation of the characteristic voltage at the bitline comprises dynamically charging or discharging the bitline through the memory cell.
A method for reading a memory cell, comprising:
- generating a characteristic voltage at a bitline connected to a first terminal of the memory cell by applying a second voltage at a second terminal of the memory cell, and a select voltage at a third terminal of the memory cell, wherein the memory cell comprises a remanently-polarizable layer and is writable into one of at least two memory states, wherein a first memory state of the at least two memory states has a first threshold voltage associated therewith and wherein a second memory state of the at least two memory states has a second threshold voltage associated therewith, wherein the first threshold voltage is different from the second threshold voltage, wherein the characteristic voltage is a function of the first threshold voltage and the second threshold voltage and represents a memory state of the memory cell, and wherein generating the characteristic voltage at the bitline comprises dynamically charging or discharging the bitline through the memory cell, and
- determining the memory state of the memory cell based on sensing the characteristic voltage.
Dependencies are inferred from the claim text.