Dynamic random access memory (DRAM) device, memory controller therefor, and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsSeung-Jun Shin, Tae-Young Oh
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
Claims20
A dynamic random access memory (DRAM) device comprising:
- a memory cell array;
- and
- a control logic configure to receive a first command that includes a first portion and a second portion;
- wherein the control logic sequentially receives the first portion and the second portion in a first mode, and
- wherein the control logic receives the second portion within a predetermined duration after receiving the first portion, and receives a second command between the first portion and the second portion in a second mode.
A memory controller to control a dynamic random access memory (DRAM) device, the memory controller comprising:
- a control logic configured to transmit a first command that includes a first portion and a second portion, and to selectively operate in a first mode or a second mode;
- and
- a transmitter configured to transmit the first portion and the second portion of the first command continuously during a plurality of clock cycles in the first mode, and to transmit a second command between the first portion and the second portion of the first command in the second mode.
A memory system, comprising:
- a memory device configured to receive a first command that includes a first portion and a second portion;
- and
- a memory controller configured to transmit the first portion and the second portion of the first command continuously during a plurality of clock cycles in a first mode, or to transmit a second command between the first portion and the second portion of the first command in a second mode.
Dependencies are inferred from the claim text.