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US 11,081,151 B2Granted
Techniques to improve a read operation to a memory array
AssigneeIntel Corporation
InventorDavide Mantegazza
Life of this patent
Estimating the term…
Abstract
Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.
Claims15
An apparatus comprising:
- an interface to access memory cells of a cross-point memory array of a memory device, the cross-point memory array includes memory cells located at an intersection of bit-lines and word-lines, the bit-lines to have at least one bit-line electrode to provide voltage to the bit-lines, the word-lines to have at least one word-line electrode to provide voltage to the word-lines;
- and
- a controller for the memory device, the controller to include logic, at least a portion of which is implemented as hardware, the logic to:
- identify a first portion of memory cells of the cross-point memory array as having a first characteristic to set a first read reference voltage or current to detect a memory state of memory cells included in the first portion of memory cells during read operations to the cross-point memory array;
- and
- identify a second portion of memory cells of the cross-point memory array as having a second characteristic to set a second read reference voltage or current to detect a memory state of memory cells included in the second portion of memory cells during read operations to the cross-point memory array,
- wherein the memory cells included in the first and second portions of memory cells are to separately include resistive memory elements to maintain a SET state or a RESET state, a detected SET state for targeted memory cells included in the first portion of memory cells based on detection of a voltage or current during a read operation to the targeted memory cells included in the first portion of memory cells that exceeds the first read reference voltage or current, a detected SET state for targeted memory cells included in the second portion of memory cells based on detection of a voltage or current during a read operation to the targeted memory cells included in the first portion that exceeds the second read reference voltage or current.
4 more elements
A method comprising:
- identifying a first portion of memory cells of a cross-point memory array including memory cells located at an intersection of bit-lines and word-lines, the bit-lines having at least one bit-line electrode to provide voltage to the bit-lines, the word-lines having at least one word-line electrode to provide voltage to the word-lines, the first portion of memory cells identified based on having a first characteristic to set a first read reference voltage or current to detect a memory state of memory cells included in the first portion or memory cells during read operations to the cross-point memory array;
- and
- identifying a second portion of memory cells of the cross-point memory array based on the second portion of memory cells having a second characteristic to set a second read reference voltage or current to detect a memory state of memory cells included in the second portion of memory cells during read operations to the cross-point memory array,
- wherein the memory cells included in the first and second portions of memory cells are to separately include resistive memory elements to maintain a SET state or a RESET state, a detected SET state for targeted memory cells included in the first portion of memory cells based on detection of a voltage or current during a read operation to the targeted memory cells included in the first portion of memory cells that exceeds the first read reference voltage or current, a detected SET state for targeted memory cells included in the second portion of memory cells based on detection of a voltage or current during a read operation to the targeted memory cells included in the first portion that exceeds the second read reference voltage or current.
1 more element
A system comprising:
- a cross-point memory array of a memory device, the cross-point memory array includes memory cells located at an intersection of bit-lines and word-lines, the bit-lines to have at least one bit-line electrode to provide voltage to the bit-lines, the word-lines to have at least one word-line electrode to provide voltage to the word-lines;
- an interface to access memory cells of the cross-point memory array;
- and
- a controller coupled with the interface, the controller to include logic, at least a portion of which is implemented as hardware, the logic to:
- identify a first portion of memory cells of the cross-point memory array as having a first characteristic to set a first read reference voltage or current to detect a memory state of memory cells included in the first portion of memory cells during read operations to the cross-point memory array;
- and
- identify a second portion of memory cells of the cross-point memory array as having a second characteristic to set a second read reference voltage or current to detect a memory state of memory cells included in the second portion of memory cells during read operations to the cross-point memory array,
- wherein the memory cells included in the first and second portions of memory cells are to separately include resistive memory elements to maintain a SET state or a RESET state, a detected SET state for targeted memory cells included in the first portion of memory cells based on detection of a voltage or current during a read operation to the targeted memory cells included in the first portion of memory cells that exceeds the first read reference voltage or current, a detected SET state for targeted memory cells included in the second portion of memory cells based on detection of a voltage or current during a read operation to the targeted memory cells included in the first portion that exceeds the second read reference voltage or current.
5 more elements
Dependencies are inferred from the claim text.