Binary weighted voltage encoding scheme for supporting multi-bit input precision
AssigneeSanDisk Technologies LLC
InventorsWon Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
Life of this patent
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Abstract
An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.
Claims20
A non-volatile memory device, comprising:
- a plurality of N input lines;
- one or more conductive lines, including a first conductive line;
- a plurality of memory cells, including a first plurality of N memory cells each connected between the first conductive line and a corresponding one of the input lines and each configured to store a first weight value of a neural network as a binary value;
- and
- one or more control circuits connected to the input lines and the conductive lines and configured to:
- receive an N-bit input value for the neural network;
- convert the input value into a plurality of N voltage values;
- concurrently apply each of the N voltage values to a corresponding one of the input lines;
- and
- determine a resultant current in the first conductive line in response to concurrently applying each of the N voltages to the corresponding one of the input lines.
A method, comprising:
- receiving an N-bit input value for a neural network;
- converting the input value into a plurality of N voltage values, each of the voltage values corresponding to a bit of the input value;
- concurrently applying each of the N voltages to a corresponding one of a plurality of N input lines of an array of memory cells, the array including a first set of N memory cells each connected between a first conductive line and a corresponding one of the input lines, each memory cell of the first set storing a first weight value of the neural network as a binary value;
- and
- determining a resultant current in the first conductive line in response to concurrently applying the N voltage values to the corresponding input lines.
An apparatus, comprising:
- one or more control circuits configured to connect to a plurality of memory cells each connected between one of a plurality of word lines and one of one or more bit lines, the one or more control circuits configured to:
- receive an N-bit input value for a neural network;
- convert the input value into a plurality of voltage values;
- concurrently apply each of the voltage values to a corresponding one of the word lines;
- and
- determine a product of the N-bit input value for the neural network and a first bit value of a weight value for the neural network by measuring a resultant current in a first bit line connected to a first subset of the memory cells each storing the first bit value and each connected between a corresponding one of the plurality of word lines and the first of the bit line.
Dependencies are inferred from the claim text.