Common voltage compensation circuit unit, display panel, display device, and common voltage compensation method for display panel

A display panel, comprising

• a plurality of cascaded common voltage compensation circuit units, each of the common voltage compensation circuit units comprising:
• a trigger signal terminal,
• a common voltage output terminal, a design common voltage signal terminal, a power signal terminal, a compensation common voltage signal terminal, a reset signal terminal, a clock signal terminal, a trigger signal input sub-circuit, a first output sub-circuit, a control sub-circuit, a second output sub-circuit, and a reset sub-circuit, wherein:
• an input terminal of the trigger signal input sub-circuit is electrically connected to the trigger signal terminal, an output terminal of the trigger signal input sub-circuit is electrically connected to a first node, and the trigger signal input sub-circuit is configured to, in response to receiving a first level signal at the input terminal of the trigger signal input sub-circuit, bring the input terminal of the trigger signal input sub-circuit into conduction with the output terminal of the trigger signal input sub-circuit;
• an input terminal of the first output sub-circuit is electrically connected to the compensation common voltage signal terminal, a control terminal of the first output sub-circuit is electrically connected to the first node, an output terminal of the first output sub-circuit is electrically connected to the common voltage output terminal, and the first output sub-circuit is configured to, in response to receiving a third level signal at the control terminal of the first output sub-circuit, bring the input terminal of the first output sub-circuit into conduction with the output terminal of the first output sub-circuit, wherein an absolute value of the third level signal is greater than or equal to an absolute value of the first level signal, and the third level signal and the first level signal have a same polarity;
• a first control terminal of the control sub-circuit is electrically connected to the clock signal terminal, a second control terminal of the control sub-circuit is electrically connected to a second output terminal of the reset sub-circuit, a first input terminal of the control sub-circuit is electrically connected to the clock signal terminal, a second input terminal of the control sub-circuit is electrically connected to the trigger signal terminal, a first output terminal of the control sub-circuit is electrically connected to the first node, a second output terminal of the control sub-circuit is electrically connected to a second node, and the control sub-circuit is configured to, in response to receiving the first level signal at the first control terminal of the control sub-circuit, bring the second input terminal of the control sub-circuit into conduction with the first output terminal of the control sub-circuit, and in response to receiving a second level signal at the second control terminal of the control sub-circuit, disconnect the first input terminal of the control sub-circuit from the second output terminal of the control sub-circuit;
• a first control terminal of the second output sub-circuit is electrically connected to the second node, a second control terminal of the second output sub-circuit is electrically connected to the reset signal terminal, a third control terminal of the second output sub-circuit is electrically connected to the clock signal terminal, an input terminal of the second output sub-circuit is electrically connected to the design common voltage signal terminal, an output terminal of the second output sub-circuit is electrically connected to the common voltage output terminal, and the second output sub-circuit is configured to, in response to receiving the first level signal at at least one of the first control terminal, the second control terminal, or the third control terminal of the second output sub-circuit, bring the input terminal of the second output sub-circuit into conduction with the output terminal of the second output sub-circuit;
• a first control terminal of the reset sub-circuit is electrically connected to the reset signal terminal, a second control terminal of the reset sub-circuit is electrically connected to the second node, a third control terminal of the reset sub-circuit is electrically connected to the first node, an input terminal of the reset sub-circuit is electrically connected to the power signal terminal, a first output terminal of the reset sub-circuit is electrically connected to the first node, a third output terminal of the reset sub-circuit is electrically connected to the second node, and the reset sub-circuit is configured to, in response to receiving the first level signal at at least one of the first control terminal or the second control terminal of the reset sub-circuit, bring the input terminal of the reset sub-circuit into conduction with the first output terminal of the reset sub-circuit, and in response to receiving the first level signal at the third control terminal of the reset sub-circuit, bring the input terminal of the reset sub-circuit into conduction with the second output terminal and the third output terminal of the reset sub-circuit;
• a plurality of gate lines, a plurality of common electrode lines,
• a first clock signal line,
• a second clock signal line,
• a power signal line,
• a design common voltage signal line, and
• a compensation common voltage signal line, wherein:
• the common voltage output terminal of each of the common voltage compensation circuit units is electrically connected to a corresponding one of the common electrode lines, the trigger signal terminal of each of the common voltage compensation circuit units is electrically connected to a corresponding one of the gate lines, the reset signal terminal of each of the common voltage compensation circuit units is electrically connected to another corresponding one of the gate lines, the power signal terminal of each of the common voltage compensation circuit units is electrically connected to the power signal line, the design common voltage signal terminal of each of the common voltage compensation circuit units is electrically connected to the design common voltage signal line, and the compensation common voltage signal terminal of each of the common voltage compensation circuit units is electrically connected to the compensation common voltage signal line;
• in a case that one of the common voltage compensation circuit units corresponds to an odd-row common electrode line, the clock signal terminal of the common voltage compensation circuit unit is electrically connected to the first clock signal line;
• in a case that one of the common voltage compensation circuit units corresponds to an even-row common electrode line, the clock signal terminal of the common voltage compensation circuit unit is electrically connected to the second clock signal line;
• the compensation common voltage signal line is electrically connected to a common voltage generating chip configured to provide a design common voltage signal to the compensation common voltage signal line in response to the first clock signal line or the second clock signal line connected to the clock signal terminal of the common voltage compensation circuit unit providing the first level signal, and provide a compensation common voltage signal to the compensation common voltage signal line in response to the first clock signal line or the second clock signal line connected to the clock signal terminal of the common voltage compensation circuit unit providing the second level signal.