Display device controlling an output timing of a data signal

A display device comprising:

• a signal controller configured to provide a frame control signal, and data comprising image data output in an active period and training data output in a blank period;
• a display panel comprising first to m-th data line groups, where m is a positive integer of 2 or greater;
• and
• a data driver comprising first to m-th data driving circuit units electrically connected to first to m-th data line groups in one-to-one correspondence,
• wherein each of the first to m-th data driving circuit units comprises a clock adjustment unit configured to use the frame control signal and a first clock signal to generate a second clock signal for controlling an output timing of a data signal corresponding to the image data, and
• wherein the frame control signal has a waveform having a low level in the blank period, and swinging between the low level and a high level in the active period.

A display device comprising:

• a display panel comprising first to m-th data line groups, where in is a positive integer of 2 or greater;
• and
• a data driver comprising first to m-th data driving circuit units electrically connected to first to m-th data line groups in one-to-one correspondence,
• wherein at least one v-th data driving circuit unit, where y is an integer of 2 to m, among the first to m-th data driving circuit units, comprises a timing controller configured to receive a control signal from a (y-1)-th data driving circuit unit and generate control-delayed signals using the control signal, and
• wherein each of the first to in-th data line groups is divided into x channels, where x is an integer of 2 or greater, and the control signal controls an output timing of a data signal corresponding to the data to be transmitted to an (x-k)-th channel, where k is an integer of 1 to (x-1), of the (y-1)-th data driving circuit unit.