Shift register, gate driving circuit, display device and gate driving method

A gate driving method based on a shift register, the shift register comprising an input circuit, an inverter circuit and an output circuit, the input circuit, the inverter circuit and the output circuit being coupled to a pull-up node, and the output circuit and the inverter circuit being coupled to a pull-down node, wherein

• the input circuit is configured to control a voltage at the pull-up node in response to an input signal;
• the inverter circuit is configured to invert the voltage at the pull-up node and output the inverted voltage to the pull-down node;
• and
• the output circuit is configured to output a multi-pulse signal within a duration of one frame under control of the voltage at the pull-up node and a voltage at the pull-down node,
• wherein the input circuit comprises a display pre-charge reset circuit, a sensing cascade circuit and a sensing pre-charge reset circuit;
• the sensing cascade circuit and the sensing pre-charge reset circuit are coupled to a sensing cascade node, and the display pre-charge reset circuit, the sensing pre-charge reset circuit and the output circuit are coupled to the pull-up node;
• the display pre-charge reset circuit is coupled to a first signal input terminal, a reset signal terminal, a first power supply terminal and a second power supply terminal, and is configured to write a first operating voltage in an active level state provided by the first power supply terminal to the pull-up node in response to control of a first input signal provided by the first signal input terminal in a display pre-charge period, and to write a second operating voltage in an inactive level state provided by the second power supply terminal to the pull-up node in response to control of a reset signal provided by the reset signal terminal in a display reset period;
• the sensing cascade circuit is coupled to a second signal input terminal and a second clock signal terminal, and is configured to write a second input signal in an active level state provided by the second signal input terminal to the sensing cascade node in response to control of a second clock signal provided by the second clock signal terminal in a sensing cascade period;
• the sensing pre-charge reset circuit is coupled to a first clock signal terminal, the second clock signal terminal, a third clock signal terminal and the second power supply terminal, and is configured to write a third clock signal in an active level state provided by the third clock signal terminal to the pull-up node in response to control of a voltage at the sensing cascade node and a first clock signal provided by the first clock signal terminal in a sensing pre-charge period, and to write the second operating voltage in an inactive level state provided by the second power supply terminal to the pull-up node in response to control of the second clock signal provided by the second clock signal terminal in a sensing reset period;
• wherein the output circuit is coupled to at least one signal output terminal and includes at least one output sub-circuit in one-to-one correspondence with the at least one signal output terminal, wherein an output sub-circuit of the at least one output sub-circuit is coupled to the pull-up node, the pull-down node, a corresponding signal output terminal, a corresponding driving clock signal terminal and a corresponding reset power supply terminal, is configured to write a driving clock signal provided by the corresponding driving clock signal terminal to the corresponding signal output terminal in response to control of the voltage at the pull-up node in an active level state in a display output period and a sensing output period, and is configured to write a reset operating voltage in an inactive level state provided by the corresponding reset power supply terminal to the corresponding signal output terminal in response to control of the voltage at the pull-down node in an active level state in the display reset period and the sensing reset period;
• and
• wherein the gate driving method comprises:
• in the sensing cascade period, writing, by the sensing cascade circuit, the second input signal in an active level state provided by the second signal input terminal to the sensing cascade node in response to the control of the second clock signal provided by the second clock signal terminal;
• in the display pre-charge period, writing, by the display pre-charge reset circuit, the first operating voltage in an active level state provided by the first power supply terminal to the pull-up node in response to the control of the first input signal provided by the first signal input terminal;
• in the display output period, writing, by the output sub-circuit, the driving clock signal provided by the corresponding driving clock signal terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node in an active level state;
• in the display reset period, writing, by the display pre-charge reset circuit, the second operating voltage in an inactive level state provided by the second power supply terminal to the pull-up node in response to the control of the reset signal provided by the reset signal terminal;
• and writing, by the output sub-circuit, the reset operating voltage in an inactive level state provided by the corresponding reset power supply terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-down node in an active level state;
• in the sensing pre-charge period, writing, by the sensing pre-charge reset circuit, the third clock signal in an active level state provided by the third clock signal terminal to the pull-up node in response to the control of the voltage at the sensing cascade node and the first clock signal provided by the first clock signal terminal;
• in the sensing output period, writing, by the output sub-circuit, the driving clock signal provided by the corresponding driving clock signal terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node in an active level state;
• and
• in the sensing reset period, writing, by the sensing pre-charge reset circuit, the second operating voltage in an inactive level state provided by the second power supply terminal to the pull-up node in response to the control of the second clock signal provided by the second clock signal terminal;
• and writing, by the output sub-circuit, the reset operating voltage in an inactive level state provided by the corresponding reset power supply terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-down node in an active level state.