Shift register unit, gate drive circuit, display device and driving method

A shift register unit, comprising a first input circuit, a first reset circuit, an anti-leakage circuit, a second input circuit, and an output circuit,

• wherein the first input circuit is connected to a first node and configured to input a first input signal to the first node in response to a first control signal;
• the first reset circuit is connected to the first node and a second node and is configured to reset the first node in response to a reset signal;
• the anti-leakage circuit is connected with the first node and the second node, and is configured to perform first control on a level of the second node under control of a level of the first node to reduce electrical leakage from the first node through the first reset circuit;
• the output circuit includes an output terminal, and is connected to the first node and configured to output an output signal to the output terminal under control of the level of the first node;
• and
• the second input circuit is connected to the first node and configured to input a second input signal to the first node according to a second control signal,
• wherein the second input circuit comprises an electronic charging circuit, a storage sub-circuit, and an isolation sub-circuit,
• wherein the electronic charging circuit is connected to a blanking node and configured to input the second control signal to the blanking node in response to a third clock signal;
• the storage sub-circuit is connected to the blanking node and configured to store a level of the second control signal input by the electronic charging circuit;
• and
• the isolation sub-circuit is connected to the blanking node and the first node, and is configured to input the second input signal to the first node under control of both a level of the blanking node and a second clock signal.