Shift register unit and driving method thereof, gate driver, display panel and display device

A shift register unit, comprising:

• an input terminal configured to receive an input pulse;
• a first voltage terminal configured to receive a first voltage;
• a second voltage terminal configured to receive a second voltage;
• a first clock terminal configured to receive a first clock signal;
• a second clock terminal configured to receive a second clock signal;
• an output terminal configured to output an output signal;
• an input circuit configured to, in response to the first clock signal received at the first clock terminal being active, bring the second voltage terminal into conduction with a first node, and bring the input terminal into conduction with a second node;
• a control circuit configured to, in response to the second clock signal received at the second clock terminal being active and a potential of the second node being at active potential, change a potential of the first node to inactive potential;
• and
• an output circuit configured to, in response to the potential of the first node being at active potential, bring the first voltage terminal into conduction with the output terminal, and in response to the potential of the second node being at active potential, bring the second clock terminal into conduction with the output terminal.