Gate control unit, driving method thereof, gate driver on array and display apparatus

A driving method of a shift register unit, the shift register unit comprising a shift register circuit and N output control circuits, wherein the N output circuits are electrically connected with N control signal terminals in a one-to-one correspondence and with N gate lines in a one-to-one correspondence respectively, the method comprises an input stage and an output stage, the output stage comprising N sub-output stages;

• wherein, in the input stage, an input signal terminal provides an input signal of a first potential to charge the shift register circuit;
• in the output stage, a clock signal terminal provides a clock signal of a first potential, and the shift register circuit outputs a gate driving signal to an output node under control of the clock signal;
• and
• in an i-th sub-output stage of the N sub-output stages, an i-th control signal terminal of the N control signal terminals provides an i-th control signal of a first potential, and an i-th output control circuit outputs the gate driving signal to an i-th gate line of the N gate lines under control of the i-th control signal,
• wherein the N control signal terminals sequentially output a control signal of a first potential, and the first potential is an effective potential,
• wherein the shift register unit further comprises N reset circuits, and the N reset circuits are electrically connected with N reset signal terminals in a one-to-one correspondence and the N gate lines in a one-to-one correspondence respectively, the method further comprises N reset stages;
• wherein, in an i-th reset stage of the N reset stages, an i-th reset signal terminal in the N reset signal terminals provides an i-th reset signal of a first potential, and an i-th reset circuit in the N reset circuits outputs a power supply signal from a power supply signal terminal to the i-th gate line under control of the i-th reset signal, wherein the power supply signal is a second potential;
• and
• wherein, among first (N-1) reset signal terminals of the N reset signal terminals, the i-th reset signal terminal is directly electrically connected with an (i±1)-th gate line of the N gate lines;
• and among first (N-1) reset stages of the N reset stages, the i-th reset stage and an (i÷1)-th sub-output stage in the N sub-output stages are simultaneously executed.