Compute optimization mechanism

A graphics processing system comprising:

• a graphics memory device;
• a memory controller coupled to the graphics memory device;
• a level-two (L2) cache memory coupled with the memory controller and the graphics memory device;
• and
• a multiprocessor coupled to the memory controller, the multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading, the multiprocessor including a scheduler, a plurality of processing cores, and a shared memory coupled to the plurality of processing cores, wherein the scheduler is a hardware scheduler to schedule an instruction for execution by the plurality of processing cores and the plurality of processing cores include a mixed precision core to perform a mixed precision matrix multiply and accumulate operation in response to the instruction, wherein to perform the mixed precision matrix multiply and accumulate operation, the mixed precision core is to perform an operation D=A*B+C, wherein A, B, C, and D are matrix elements, A and B are 8-bit integer elements, and C is a 32-bit integer element, and wherein the instruction is to specify a first format for matrix elements A and B, separately specify a second format for matrix element C, and the mixed precision core is to perform the operation according to the specified formats.

A method comprising:

• decoding an instruction into a decoded instruction for execution by a graphics processor including a multiprocessor coupled to a memory controller and a level-two (L2) cache memory coupled with the memory controller, the multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading, wherein the multiprocessor includes a scheduler, a plurality of processing cores, and a shared memory coupled to the plurality of processing cores, and wherein the plurality of processing cores include a mixed precision core to perform a mixed precision matrix multiply and accumulate operation;
• scheduling the decoded instruction for execution by the multiprocessor;
• and
• executing the decoded instruction via the mixed precision core, wherein the mixed precision core, in response to the instruction is to perform the mixed precision matrix multiply and accumulate operation and wherein performing the matrix multiply and accumulate operation includes performing an operation D=A*B+C, wherein A, B, C, and D are matrix elements, A and B are 8-bit integer elements, and C is a 32-bit integer element, and wherein the instruction specifies a first format for matrix elements A and B, separately specifies a second format for matrix element C, and the mixed precision core performs the operation according to the specified formats.