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US 11,080,810 B2Granted
Dynamically reconfigurable memory subsystem for graphics processors
AssigneeIntel Corporation
InventorsWenyin Fu, Abhishek R. Appu, Bhushan M. Borole, Altug Koker, Nikos Kaburlasos, Kamal Sinha
Life of this patent
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Abstract
By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.
Claims26
A method comprising:
- identifying information about a recurring pattern of usage of a storage included in a graphics processor, comprising identifying a plurality of repeated render pass sequences comprising a first pass followed by a second pass followed by a third pass, at least some of the plurality of repeated render pass sequences having different bandwidths, each of the first pass, the second pass and the third pass comprising a recognizable sequence of render operations;
- using said identified information to predict a future usage of said storage comprising predicting, for the third pass of the plurality of repeated render pass sequences, a high bandwidth;
- and
- adapting a configuration of said storage during run time by changing a number of interconnects to be powered up and traversed in said storage based on said identified information.
1 more element
One or more non-transitory computer readable media storing instructions to perform a sequence comprising:
- identifying information about a recurring pattern of usage of a storage included in a graphics processor, comprising identifying a plurality of repeated render pass sequences comprising a first pass followed by a second pass followed by a third pass, at least some of the plurality of repeated render pass sequences having different bandwidths, each of the first pass, the second pass and the third pass comprising a recognizable sequence of render operations;
- using said identified information to predict a future usage of said storage comprising predicting, for the third pass sequence of the plurality of repeated render pass sequences, a high bandwidth;
- and
- adapting a configuration of said storage during run time by changing a number of interconnects to be powered up and traversed in said storage based on said identified information.
1 more element
An apparatus comprising:
- a processor to identify information about a recurring pattern of usage of a storage in a graphics processor, comprising to identify a plurality of repeated render pass sequences comprising a first pass followed by a second pass followed by a third pass, at least some of the plurality of repeated render pass sequences having different bandwidths, each of the first pass, the second pass and the third pass comprising a recognizable sequence of render operations, use said identified information to predict a future usage of said storage comprising to predict, for the third pass of the plurality of repeated render pass sequences, a high bandwidth, and adapt a configuration of said storage during run time by changing a number of interconnects to be powered up and traversed in said storage based on said identified information;
- and
- a memory coupled to said processor.
Dependencies are inferred from the claim text.