Method for improved cut metal patterning

A system for preparing an integrated circuit device design comprising:

• a first memory configured for storing a plurality of device cell designs;
• a processor configured and programmed for
• retrieving a first device cell design and a second device cell design from the memory;
• arranging the first and second device cells in a vertically abutting configuration in an initial device layout;
• identifying a first internal metal cut in the first device cell design and a first safe region on the first device cell design;
• identifying a second internal metal cut in the second device cell design;
• determining a horizontal spacing between the first internal metal cut and the second internal metal cut in the initial device layout;
• determining whether the horizontal spacing satisfies a spacing threshold;
• and
• if the spacing threshold is not satisfied, shifting the second cell design horizontally relative to the first cell design to place the second internal metal cut under the first safe zone and thereby define a modified device layout;
• and
• evaluating the modified device layout to ensure that the spacing threshold is satisfied.

A system for manufacturing an integrated circuit device comprising:

• a first memory configured for storing a plurality of device cell designs;
• a processor configured for
• retrieving a first device cell design and a second device cell design from the memory;
• arranging the first and second device cells in a vertically abutting configuration in an initial device layout;
• identifying a first internal metal cut in the first device cell design;
• identifying a second internal metal cut in the second device cell design;
• determining a horizontal spacing between the first internal metal cut and the second internal metal cut in the initial device layout;
• determining whether the horizontal spacing satisfies a spacing threshold;
• and
• if the spacing threshold is not satisfied, shifting the second cell design horizontally relative to the first cell design by a distance equal to N contacted polysilicon pitch (CPP) to define a modified device layout, wherein N is an integer;
• and
• repeating the determining, evaluating, and shifting operations until the modified device layout satisfies the spacing threshold;
• a second memory configured for storing the modified device layout;
• a mask house configured for retrieving the modified device layout from the second memory and fabricating a plurality of masks corresponding to the modified device layout.