Method of modeling high speed channel in semiconductor package, method of designing semiconductor package using the same and method of manufacturing semiconductor package using the same

A method of designing a semiconductor package, the method comprising:

• generating a design of at least one semiconductor device that is included in the semiconductor package;
• generating a design of a high speed channel that is included in the semiconductor package;
• modeling the high speed channel;
• and
• analyzing and verifying a result of the modeling of the high speed channel,
• wherein the high speed channel comprises a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate,
• wherein modeling the high speed channel comprises:
• receiving design information of the high speed channel;
• dividing the design information into a first layout comprising the plurality of first connection wirings and a second layout comprising the plurality of through electrodes;
• performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool;
• performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and wherein the second modeling tool is different from the first modeling tool;
• and
• obtaining an integrated modeling result of an entirety of the high speed channel by combining a result of the first modeling operation and a result of the second modeling operation,
• wherein, in response to determining that the high speed channel does not satisfy a predetermined characteristic based on the analyzing and verifying the result of the modeling of the high speed channel, an operation of changing the design of the at least one semiconductor device and/or the design of the high speed channel is performed on the semiconductor package.

A method of manufacturing a semiconductor package, the method comprising:

• generating a design of a semiconductor package comprising at least one semiconductor device and a high speed channel;
• and
• fabricating the semiconductor package based on a result of designing the semiconductor package,
• wherein designing the semiconductor package comprises:
• generating a design of the at least one semiconductor device;
• generating a design of the high speed channel;
• modeling the high speed channel;
• and
• analyzing and verifying a result of the modeling of the high speed channel,
• wherein the high speed channel comprises a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes that extend within the semiconductor substrate,
• wherein modeling the high speed channel comprises:
• receiving design information of the high speed channel;
• dividing the design information into a first layout comprising the plurality of first connection wirings and a second layout comprising the plurality of through electrodes;
• performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool;
• performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout, wherein the second modeling scheme is different from the first modeling scheme, and wherein the second modeling tool is different from the first modeling tool;
• and
• obtaining an integrated modeling result of an entirety of the high speed channel by combining a result of the first modeling operation and a result of the second modeling operation.