Computational wafer inspection

A method for a device manufacturing process involving processing a portion of a design layout onto substrates, the method comprising:

• obtaining a pattern from a portion of a design layout for processing onto a substrate by a device manufacturing process;
• determining or obtaining a sensitivity of the pattern with respect to a processing parameter of the device manufacturing process for the pattern;
• and
• determining or predicting, using the sensitivity and by a computer hardware system, an existence, a probability of existence, a characteristic, or a combination selected therefrom, of a defect produced from the pattern using the device manufacturing process.

A non-transitory computer readable medium having instructions recorded thereon, the instructions, when executed by a computer system, configured to cause the computer system at least to:

• obtain information regarding a pattern from a portion of a design layout to be processed onto a substrate by a device manufacturing process, the pattern having a sensitivity to a processing parameter of the device manufacturing process for the pattern;
• obtain an actual value of the processing parameter as obtained in an execution of the device manufacturing process;
• and
• determine, based on the actual value and the sensitivity, an area of the substrate to inspect using an inspection apparatus.