Lithography simulation method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu An Tien, Hsu-Ting Huang, Ru-Gun Liu, Shih-Hsiang Lo
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Abstract
In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.
Claims20
A method of optimizing a lithography model in a lithography simulation, the method comprising:
- forming a mask in accordance with a given layout;
- printing a wafer by optical lithography using the mask;
- measuring a pattern formed on the printed wafer;
- simulating a wafer pattern using a wafer edge bias table and the given layout;
- obtaining a difference between the simulated wafer pattern and the measured pattern;
- and
- adjusting the wafer edge bias table according to the difference, thereby generating an adjusted wafer edge bias table,
- wherein the wafer edge bias table comprises at least one selected from the group consisting of a scalar value corresponding to each pattern of the given layout, the scalar value being dependent on a geometry feature of a respective pattern, a location of the respective pattern relative to the given layout, and a geometry feature of a neighboring pattern neighboring the respective pattern.
A method of manufacturing a semiconductor device, the method comprising:
- (i) forming a test mask in accordance with a test layout;
- (ii) printing a test wafer pattern by optical lithography using the test mask;
- (iii) measuring the test wafer pattern;
- (iv) simulating a pattern using a wafer edge bias table for the test layout;
- (v) obtaining a difference between the simulated pattern and the measured test wafer pattern;
- repeating (i)-(v) until the difference between the simulated pattern and the measured test wafer pattern is smaller than a threshold or a limit for a number of iterations has been reached, thereby obtaining an adjusted wafer edge bias table;
- obtaining optical proximity correction (OPC) data by performing OPC to a circuit pattern using the adjusted wafer edge bias table;
- manufacturing a photomask using the obtained OPC data;
- and
- manufacturing a semiconductor device using the photomask.
A lithography simulator comprising:
- a non-transitory computer-readable memory storing a program and a wafer edge bias table;
- and
- a processor operatively coupled with the memory,
- wherein the program, when executed by the processor, causes the processor to perform a lithography simulation using the wafer edge bias table,
- wherein the wafer edge bias table comprises at least one selected from the group consisting of a scalar value corresponding to each pattern of the given layout, the scalar value being dependent on a geometry feature of the respective pattern;
- a location of the respective pattern relative to the given layout;
- and a geometry feature of a neighboring pattern neighboring the respective pattern.
Dependencies are inferred from the claim text.