Automated design closure with abutted hierarchy

A computer comprising:

• a memory;
• and
• at least one processor, coupled to said memory, and operative to increase the efficiency of electronic design automation by:
• executing partition-aware global routing with track assignment on an electronic data structure comprising a small block floorplan of a putative integrated circuit design, the small block floorplan being virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks, wherein a high cost is assigned to a route that crosses a same border twice and wherein said executing of said global routing includes applying a cost function that utilizes said assigned high cost to prevent zig-zagging of routes;
• based on results of said executing, determining locations, on said inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in said routing, as well as required sizes of said ports;
• generating a physical partitioning based on said inter-large-block boundaries;
• aligning said ports with said inter-large-block boundaries;
• and
• generating a hardware description language design structure encoding said physical partitioning.

A non-transitory computer readable medium comprising computer executable instructions which when executed by a computer performing electronic design automation cause the computer to perform a method which increases the efficiency of the electronic design automation, the method comprising:

• executing partition-aware global routing with track assignment on an electronic data structure comprising a small block floorplan of a putative integrated circuit design, the small block floorplan being virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks, wherein a high cost is assigned to a route that crosses a same border twice and wherein said executing of said global routing includes applying a cost function that utilizes said assigned high cost to prevent zig-zagging of routes;
• based on results of said executing, determining locations, on said inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in said routing, as well as required sizes of said ports;
• generating a physical partitioning based on said inter-large-block boundaries;
• aligning said ports with said inter-large-block boundaries;
• and
• generating a hardware description language design structure encoding said physical partitioning.