Layout design of integrated circuit with through-substrate via

A method, comprising:

• generating an integrated circuit (IC) layout design, comprising:
• generating a pattern of a through-substrate via (TSV) region;
• generating a pattern of active regions of active devices around the pattern of the TSV region, wherein the active devices are arranged in groups and are separated from the TSV region by a keep-out-zone (KOZ);
• generating a pattern of active regions of dummy devices in the KOZ, wherein the dummy devices are arranged in groups;
• defining the separation between the TSV region, the active regions of active devices and the active regions of dummy devices as a shallow trench isolation (STI) region;
• wherein areas of each of the groups of dummy devices defined by the active regions in each group of dummy devices have substantially identical dimension in a first direction, and
• manufacturing an IC based on the IC layout design.

A method, comprising:

• generating an integrated circuit (IC) layout design, comprising:
• generating a pattern of a shallow trench isolation (STI) region to define a pattern of a through-substrate via (TSV) region, a pattern of active regions in a first dummy device region surrounding the TSV region, a pattern of active regions in a second dummy device region surrounding the first dummy device region, and a pattern of active regions in an active device region located between the first dummy region and the second dummy region;
• generating gate patterns over the STI region, the active regions in the first dummy device region, the active regions in the second dummy device region, and the active regions in the active device region;
• wherein each of the active regions of the first dummy device region has substantially identical dimension in a first direction, and
• manufacturing an IC based on the IC layout design.