Integrated circuit, system, and method of forming the same

A system for designing an integrated circuit, the system comprises:

• a non-transitory computer readable medium configured to store executable instructions;
• and
• a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for:
• arranging first conductive feature layout patterns in a cell region, wherein the first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction different from the first direction;
• arranging second conductive feature layout patterns in the cell region, wherein the second conductive feature layout patterns extend in the first direction, and the first and second conductive feature layout patterns are alternately arranged in the second direction;
• and
• arranging first cut feature layout patterns on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns, wherein one of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction.

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• generating a first conductive feature layout pattern in a cell region, wherein the first conductive feature layout pattern extends in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction different from the first direction;
• generating a second conductive feature layout pattern in the cell region and adjacent to the first conductive feature layout pattern, wherein the second conductive feature layout pattern extends in the first direction;
• generating a first cut feature layout pattern on the first cell boundary of the cell region and on an end of the first conductive feature layout pattern;
• generating a second cut feature layout pattern on the first cell boundary of the cell region and on an end of the second conductive feature layout pattern;
• generating a via pattern on the first conductive feature layout pattern, spaced apart from the first cut feature layout pattern, and overlapping with the second cut feature layout pattern;
• and
• generating the IC layout diagram comprising the first and second conductive feature layout patterns, the first and second cut feature layout patterns, and the via pattern.