US 11,080,444 B1Granted

Concurrent fault co-simulator

AssigneeCadence Design Systems, Inc.

InventorsManoj Kumar, David J. Roberts, Apurva Kalia

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Abstract

Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.

Claims20

Dependent claims

A method comprising:

accessing, by one or more hardware processors, design data for a circuit design stored in a memory, the circuit design comprising a plurality of machine regions;
accessing, by the one or more hardware processors, a set of functional simulation data comprising test bench data for functional simulation and functional verification of the circuit design;
accessing, by the one or more hardware processors, a set of fault simulation data, the set of fault simulation data comprising a plurality of fault data for a plurality of faults to be analyzed during fault simulation;
selecting, by the one or more hardware processors, the plurality of faults for injection into a co-simulator;
selecting, by the one or more hardware processors, a set of strobe detection points for the circuit design associated with fault detection for the plurality of faults;
initiating, by the one or more hardware processors, functional simulation of the circuit design using the design data and the set of functional simulation data for a first machine region of the plurality of machine regions, wherein the first machine region is associated with at least a first fault of the plurality of faults;
computing, by the one or more hardware processors, a fault injection simulation for the first fault as a difference between an associated functional simulation of the first machine region without the first fault and an associated fault simulation of the first machine region with the first fault, the computing the fault injection simulation comprising identifying, by a concurrent analysis engine, one or more divergence points associated with the first fault to perform the associated functional simulation and the associated fault simulation;
and
outputting, by the one or more hardware processors, a functional safety result for the fault injection simulation for the first fault.

6 more elements

A device comprising:

a memory storing simulation data for a circuit design, the circuit design comprising a plurality of machine regions;
one or more processors coupled to the memory and configured for operations of co-simulation functional analysis and fault analysis of the circuit design, the operations comprising:
selecting a plurality of faults from the simulation data for injection into a co-simulator;
initiating functional simulation of the plurality of machine regions using the simulation data;
identifying a first machine region, the first machine region associated with at least a first fault of the plurality of faults;
and
computing a fault injection simulation for the first fault as a difference between an associated functional simulation of the first machine region without the first fault and an associated fault simulation of the first machine region with the first fault;
and
a concurrent engine implemented by the one or more processors, the concurrent engine configured to perform operations comprising:
identifying divergence points associated with the first fault and the first machine region;
and
performing the associated functional simulation and the associated fault simulation using the divergence points.

9 more elements

A non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processors of a device, cause the device to perform operations comprising:

accessing design data for a circuit design stored in a memory, the circuit design comprising a plurality of machine regions;
accessing a set of functional simulation data comprising test bench data for functional simulation and functional verification of the circuit design;
accessing a set of fault simulation data, the set of fault simulation data comprising a plurality of fault data for a plurality of faults to be analyzed during fault simulation;
selecting the plurality of faults for injection into a co-simulator;
selecting a set of strobe detection points for the circuit design associated with fault detection for the plurality of faults;
initiating functional simulation of the circuit design using the design data and the set of functional simulation data for a first machine region of the plurality of machine regions, wherein the first machine region is associated with at least a first fault of the plurality of faults;
computing a fault injection simulation for the first fault as a difference between an associated functional simulation of the first machine region without the first fault and an associated fault simulation of the first machine region with the first fault, the computing the fault injection simulation comprising identifying, by a concurrent analysis engine, one or more divergence points associated with the first fault to perform the associated functional simulation and the associated fault simulation;
and
outputting a functional safety result for the fault injection simulation for the first fault.

6 more elements

Dependencies are inferred from the claim text.