Hardware accelerators and methods for out-of-order processing

A method comprising:

• concurrently processing a first dataset and a second dataset with a plurality of processing elements forming a plurality of logical rows of a multidimensional processing array and a plurality of logical columns of the multidimensional processing array;
• providing a switch control value to a processing element of the plurality of processing elements;
• switching a switch of the processing element of the plurality of processing elements to selectively source, from either of an output for the first dataset from an upstream processing element of the plurality of processing elements processed by the upstream processing element or a boundary condition value for the second dataset stored in the processing element, based on the switch control value provided to the processing element;
• tracking progress of the multidimensional processing array on a first input sequence of the first dataset and a second input sequence of the first dataset, and on a third input sequence of the second dataset and a fourth input sequence of the second dataset;
• on completion of processing both the first input sequence of the first dataset and the second input sequence of the first dataset by the multidimensional processing array, sending a first result of the processing of the first input sequence of the first dataset and the second input sequence of the first dataset, a first index identifying the first input sequence, and a second index identifying the second input sequence to a processor core coupled to the plurality of processing elements;
• and
• on completion of processing both the third input sequence of the second dataset and the fourth input sequence of the second dataset by the multidimensional processing array, sending a second result of the processing of the third input sequence of the second dataset and the fourth input sequence of the second dataset, a third index identifying the third input sequence, and a fourth index identifying the fourth input sequence to the processor core coupled to the plurality of processing elements.

A hardware accelerator comprising:

• a plurality of processing elements coupled to form a plurality of logical rows of a multidimensional processing array and a plurality of logical columns of the multidimensional processing array,
• wherein a processing element of the plurality of processing elements comprises a switch to selectively source, from either of an output for a first dataset from an upstream processing element of the plurality of processing elements processed by the upstream processing element or a boundary condition value for a second dataset stored in the processing element, based on a switch control value provided to the processing element;
• and
• a controller to track progress by the multidimensional processing array on a first input sequence of the first dataset and a second input sequence of the first dataset, and on a third input sequence of the second dataset and a fourth input sequence of the second dataset, wherein the controller is to:
• on completion of processing both the first input sequence of the first dataset and the second input sequence of the first dataset by the multidimensional processing array, send a first result of the processing of the first input sequence of the first dataset and the second input sequence of the first dataset, a first index identifying the first input sequence, and a second index identifying the second input sequence as an output of the hardware accelerator, and
• on completion of processing both the third input sequence of the second dataset and the fourth input sequence of the second dataset by the multidimensional processing array, send a second result of the processing of the third input sequence of the second dataset and the fourth input sequence of the second dataset, a third index identifying the third input sequence, and a fourth index identifying the fourth input sequence as an output of the hardware accelerator.