Compiler flow logic for reconfigurable architectures

A computer-implemented method of transforming a high-level program for mapping onto a reconfigurable data processor with an array of configurable units, the method including:

• partitioning a dataflow graph of the high-level program into memory allocations and execution fragments, wherein the memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph, and the execution fragments represent operations on the data, wherein the execution fragments are executable asynchronously;
• designating the memory allocations and the execution fragments to virtual configurable units;
• partitioning the execution fragments into memory fragments and compute fragments;
• assigning the memory fragments and the compute fragments to the virtual configurable units;
• allocating the virtual configurable units to physical configurable units;
• placing the physical configurable units onto positions in the array of configurable units and routing data and control networks between the placed positions;
• and
• generating a bit file with configuration data for the placed positions and the routed data and control networks, wherein the bit file, when loaded onto an instance of the array of configurable units, causes the array of configurable units to implement the dataflow graph.

A non-transitory computer readable storage medium impressed with computer program instructions to transform a high-level program for mapping onto a reconfigurable data processor with an array of configurable units, the instructions, when executed on a processor, implement a method comprising:

• partitioning a dataflow graph of the high-level program into memory allocations and execution fragments, wherein the memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph, and the execution fragments require operations on the data, including loading the data from allocated memory and computing with the data;
• designating the memory allocations to virtual memory units and designating the execution fragments to virtual compute units;
• partitioning the execution fragments into memory fragments that load the data from the allocated memory and compute fragments that compute with the data;
• assigning the memory fragments to the virtual memory units and assigning the compute fragments to the virtual compute units;
• allocating the virtual memory units to physical memory units and allocating the virtual compute units to physical compute units;
• placing the physical memory units and the physical compute units onto positions in the array of configurable units and routing data and control networks between the placed positions;
• and
• generating a bit file with configuration data for the placed positions and the routed data and control networks, wherein the bit file, when loaded onto an instance of the array of configurable units, causes the array of configurable units to implement the dataflow graph.

A system including one or more processors coupled to memory, the memory loaded with computer instructions to transform a high-level program for mapping onto a reconfigurable data processor with an array of configurable units, the instructions, when executed on the processors, implement actions comprising:

• partitioning a dataflow graph of the high-level program into memory allocations and execution fragments, wherein the memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement of the dataflow graph, and the execution fragments represent operations on the data;
• designating the memory allocations to virtual memory units and designating the execution fragments to virtual compute units;
• partitioning the execution fragments into memory fragments and compute fragments;
• assigning the memory fragments to the virtual memory units and assigning the compute fragments to the virtual compute units;
• allocating the virtual memory units to physical memory units and allocating the virtual compute units to physical compute units, wherein allocating the virtual memory units and the virtual compute units comprises allocating at least one of the virtual memory units to multiple physical memory units and/or allocating at least one of the virtual compute units to multiple physical compute units;
• placing the multiple physical memory units and the multiple physical compute units onto positions in the array of configurable units and routing data and control networks between the placed positions;
• and
• generating a bit file with configuration data for the placed positions and the routed data and control networks, wherein the bit file, when loaded onto an instance of the array of configurable units, causes the array of configurable units to implement the dataflow graph.