Technologies for providing a scalable architecture for performing compute operations in memory
AssigneeIntel Corporation
InventorsShigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram, Jawad B. Khan
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Abstract
Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.
Claims22
A memory comprising:
- non-volatile memory media including multiple partitions;
- and
- media access circuitry coupled with the non-volatile memory media, the media access circuitry including a plurality of compute logic units and a plurality of scratch pads, each of the plurality of scratch pads corresponding to one of the multiple partitions, wherein each of the multiple partitions corresponds to one of the plurality of compute logic units;
- each of the plurality of compute logic units to:
- access data from a corresponding partition of the non-volatile memory media to perform a requested operation;
- store the data in one of the plurality of scratch pads corresponding to the partition;
- perform sub-operations of the requested operation on the data concurrently with other compute logic units of the plurality of compute logic units;
- and
- write, to the non-volatile memory media, resultant data from execution of the requested operation.
A media access circuitry comprising:
- circuitry to read matrix data from a non-volatile memory media to perform a requested operation, non-volatile memory media including multiple partitions;
- a plurality of scratch pads coupled with the circuitry to store the matrix data read from the non-volatile memory media, each of the plurality of scratch pads corresponding to one of the multiple partitions;
- a plurality of compute logic units coupled with the non-volatile memory media,
- each of the plurality of compute logic units to:
- access, concurrently with other compute logic units of the plurality of compute logic units, data from a corresponding partition of the non-volatile memory media;
- store the data in one of the plurality of scratch pads corresponding to the partition;
- perform sub-operations of the requested operation on the data concurrently with other compute logic units of the plurality of compute logic units;
- and
- write, to the non-volatile memory media, resultant data from execution of the requested operation.
A system comprising:
- a non-volatile memory module comprising one or more packages, each of the one or more packages comprising:
- non-volatile memory media including multiple partitions;
- and
- a plurality of compute logic units coupled with the non-volatile memory media and a plurality of scratch pads, each of the plurality of scratch pads corresponding to one of the multiple partitions, wherein each of the multiple partitions corresponds to one of the plurality of compute logic units;
- each of the plurality of compute logic units to:
- access, concurrently with other compute logic units of the plurality of compute logic units, data from a corresponding partition of the non-volatile memory media to perform a requested operation;
- store the data in one of the plurality of scratch pads corresponding to the partition;
- perform, concurrently with each of the plurality of compute logic units, the requested operation on the data;
- and
- write, to the non-volatile memory media, resultant data from execution of the requested operation.
Dependencies are inferred from the claim text.