US 11,080,225 B2Granted

Peer direct mechanism for direct memory access across host devices

AssigneeCisco Technology, Inc.

InventorsSagar Borikar, Anant Thakar

Life of this patent

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Abstract

In one example, at least one peripheral interconnect switch obtains, from a first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and a second endpoint device. The message indicates an address assigned to the second endpoint device by a host device as a destination of the message. Based on the address assigned to the second endpoint device by the host device, the at least one peripheral interconnect switch identifies an address assigned to the second endpoint device by the at least one peripheral interconnect switch. In response to identifying the address assigned to the second endpoint device by the at least one peripheral interconnect switch, the at least one peripheral interconnect switch provides the message to the second endpoint device.

Claims20

Dependent claims

A method comprising:

at at least one peripheral interconnect switch connected to a first host device, a second host device, a first endpoint device, and a second endpoint device, wherein the first host device hosts the first endpoint device and the second host device hosts the second endpoint device:
obtaining, from the second host device, a command to provide an indication that a direct memory access data transfer between the first endpoint device and the second endpoint device is complete;
providing the command to the second endpoint device;
obtaining, from the first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and the second endpoint device, wherein the message indicates an address assigned to the second endpoint device by the second host device as a destination of the message;
performing an address translation between based on the address assigned to the second endpoint device by the second host device, identifying an address assigned to the second endpoint device by the at least one peripheral interconnect switch based on an address mapping;
in response to identifying the address assigned to the second endpoint device by the at least one peripheral interconnect switch, providing the message to the second endpoint device;
providing, from the second endpoint device to the second host device, an indication that the direct memory access data transfer is complete;
and
providing, from the second host device to the first host device, the indication that the direct memory access data transfer is complete.

6 more elements

An apparatus comprising:

a communication interface configured to provide or obtain messages to or from a first host device, a second host device, a first endpoint device, and a second endpoint device, wherein the first host device hosts the first endpoint device and the second host device hosts the second endpoint device;
and
one or more processors coupled to the communication interface, wherein the one or more processors are configured to:
obtain, from the second host device, a command to provide an indication that a direct memory access data transfer between the first endpoint device and the second endpoint device is complete;
provide the command to the second endpoint device;
obtain, from the first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and the second endpoint device, wherein the message indicates an address assigned to the second endpoint device by the second host device as a destination of the message;
perform an address translation between based on the address assigned to the second endpoint device by the second host device, identify an address assigned to the second endpoint device by the apparatus based on an address mapping;
in response to identifying the address assigned to the second endpoint device by the apparatus, provide the message to the second endpoint device;
provide, from the second endpoint device to the second host device, an indication that the direct memory access data transfer is complete;
and
provide, from the second host device to the first host device, the indication that the direct memory access data transfer is complete.

8 more elements

One or more non-transitory computer readable storage media encoded with instructions that, when executed by a processor of at least one peripheral interconnect switch connected to a first host device, a second host device, a first endpoint device, and a second endpoint device, wherein the first host device hosts the first endpoint device and the second host device hosts the second endpoint device, cause the processor to:

obtain, from the second host device, a command to provide an indication that a direct memory access data transfer between the first endpoint device and the second endpoint device is complete;
provide the command to the second endpoint device;
obtain, from the first endpoint device, a message initiating a direct memory access data transfer between the first endpoint device and the second endpoint device, wherein the message indicates an address assigned to the second endpoint device by the second host device as a destination of the message;
perform an address translation between based on the address assigned to the second endpoint device by the second host device, identify an address assigned to the second endpoint device by the at least one peripheral interconnect switch based on an address mapping;
in response to identifying the address assigned to the second endpoint device by the at least one peripheral interconnect switch, provide the message to the second endpoint device;
provide, from the second endpoint device to the second host device, an indication that the direct memory access data transfer is complete;
and
provide, from the second host device to the first host device, the indication that the direct memory access data transfer is complete.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/356,581Filed 18 Mar 2019
Published: US 2020/0301873 A124 Sep 2020
Granted: 3 Aug 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 15/17331
Intercommunication techniques: distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
G06F 13/128
Where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine: for dedicated transfers to a network
G06F 13/28
For access to input/output bus: using burst mode transfer, e.g. direct memory access DMA, cycle steal
G06F 13/4022
Coupling between buses: using switching circuits, e.g. switching matrix, connection or expansion network