System on chip having semaphore function and method for implementing semaphore function
AssigneeSamsung Electronics Co., Ltd.
InventorsDongsik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
Life of this patent
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Abstract
A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
Claims17
A system on chip (SoC) comprising:
- a first master;
- a second master;
- an interface configured to provide communication between an external device and the first master and/or communication between the external device and the second master;
- and
- a controller configured to receive a first request to access the interface from the first master and a second request to access the interface from the second master, determine a first operational period for the first master and a second operational period for the second master, and schedule the first master to have access to the interface for the first operational period and the second master to have access to the interface for the second operational period,
- wherein the interface uses a serial data line and a serial clock line for the communication, and
- wherein the first master is driven by a real time operating system, and the second master is driven by a non-real time operating system.
A method of controlling an external device with a plurality of masters comprising:
- receiving a first request to access an interface from a first master;
- receiving a second request to access the interface from a second master;
- determining a first operational period for the first master;
- determining a second operational period for the second master;
- and
- scheduling the first master to have access to the interface for the first operational period and the second master to have access to the interface for the second operational period,
- wherein the interface is configured to provide communication between an external device and the first master and/or communication between the external device and the second master,
- wherein the interface uses a serial data line and a serial clock line for the communication, and
- wherein the first master is driven by a real time operating system, and the second master is driven by a non-real time operating system.
A system on chip (SoC) comprising:
- a plurality of masters;
- an interface configured to provide communication between an external device and the plurality of masters;
- and
- a multi-master controller configured to receive requests from the plurality of masters for accessing the interface and manage the requests by scheduling each of the plurality of masters to have access to the interface for a respective operational period,
- wherein the interface uses a serial data line and a serial clock line for the communication, and
- wherein the multi-master controller is configured to execute an atomic sequence corresponding to each of the plurality of masters.
Dependencies are inferred from the claim text.