US 11,080,218 B2 · Interface chip used to select memory chip and storage device including interface chip and memory chip

Abstract

An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an external chip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal.

Claims20

Dependent claims

An interface chip comprising:

a command decoder configured to decode a command included in data input/output signals based on a clock signal;
clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more);
clock latency circuitry configured to transmit, to an external chip, a latency clock signal including edges corresponding to second to n-th edges of the clock signal;
chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal;
and
chip enable control circuitry configured to,
receive a chip enable signal indicating a channel for the data input/output signals, and
transmit the chip enable signal to the external chip based on the chip select signal.

5 more elements

A storage device comprising:

semiconductor chips of first to n-th stages (“n” being an integer of 2 or more);
and
a controller configured to transmit data input/output signals including a command for selecting a semiconductor chip of the n-th stage, a clock signal including first to n-th edges, and a chip enable signal, to a semiconductor chip of a first stage,
wherein, when “n” is 2, based on a first edge of the clock signal, the semiconductor chip of the first stage is configured to,
receive the chip enable signal from the controller, and
transmit the chip enable signal to a semiconductor chip of the n-th stage, and
wherein, when “n” is greater than 2 or more, the semiconductor chips of first to (n−1)-th stages are configured, respectively, to,
receive the chip enable signal from the controller and the semiconductor chips of first to (n−2)-th stages, and
transmit the chip enable signal to the semiconductor chips of second to n-th stages, based on first to (n−1)-th edges of the clock signal.

6 more elements

Dependencies are inferred from the claim text.

Interface chip used to select memory chip and storage device including interface chip and memory chip

Life of this patent

Interface chip used to select memory chip and storage device including interface chip and memory chip

Life of this patent

Abstract

Claims20