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US 11,080,212 B2Granted
High performance interconnect physical layer
AssigneeIntel Corporation
InventorsVenkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
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Abstract
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
Claims26
An apparatus comprising:
- a port to couple to a device over an interconnect, wherein the port comprises protocol circuitry to establish a link on the interconnect, wherein the interconnect comprises a set of physical lanes, and the protocol circuitry is to:
- enter a partial width transmitting link state, wherein a first number of lanes in the set of lanes are to be used to communicate data on the link in the partial width transmitting link state;
- send a first packet on the link in the partial width transmitting link state, wherein the first packet is encoded by the physical layer circuitry as a first set of flits;
- send an electrical ordered set on the link to cause the link to transition from the partial width transmitting link state to a transmitting link state, wherein a second number of lanes in the set of lanes are to be used to communicate data in the transmitting link state, and the second number is greater than the first number;
- and
- send a second packet on the link during the transmitting link state, wherein the second packet is encoded by the physical layer circuitry as a second set of flits.
3 more elements
A method comprising:
- establishing a link on an interconnect based on an interconnect protocol, wherein the interconnect comprises a set of physical lanes, and the interconnect connects a first device to a second device;
- causing the link to enter a partial width transmitting link state, wherein a first subset of the set of lanes are to be active and a second subset of the set of lanes are to be asleep in the partial width transmitting link state;
- sending a first flit on the first subset of lanes in the partial width transmitting link state, wherein the first flit includes at least a portion of a first packet, and the first flit is of a defined length;
- sending an electrical ordered set on an interconnect to cause the link to transition from the partial width transmitting link state to a transmitting link state, wherein the set of lanes are to be used to communicate data in the transmitting link state;
- and
- sending a second flit on the set of lanes in the transmitting link state, wherein the second flit includes at least a portion of a second packet, and the second flit is of the defined length.
3 more elements
A system comprising:
- a host device comprising a processor core;
- and
- an endpoint device coupled to the host device by a link, wherein the link comprises a plurality of physical lanes, and the endpoint device comprises protocol circuitry to establish the link according to an interconnect protocol, and the protocol circuitry is to:
- enter a partial width transmitting link state on the link, wherein a first subset of the plurality of lanes are active and a second subset of the plurality of lanes are inactive in the partial width transmitting link state;
- send a first flit on the first subset of the plurality of lanes while in the partial width transmitting link state, wherein the first flit is sent to communicate at least a portion of a first packet to the host device;
- send an electrical ordered set followed by a defined number of consecutive training sequences in association with a transition from the partial width transmitting link state to a transmitting link state, wherein the plurality of lanes are active in the transmitting link state;
- and
- send a second flit to the host device on the plurality of lanes during the transmitting link state, wherein the second flit is sent to communicate at least a portion of a second packet to the host device.
5 more elements
Dependencies are inferred from the claim text.