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US 11,080,210 B2Granted
Memory sub-system including an in package sequencer separate from a controller
AssigneeMicron Technology, Inc.
InventorsSamir Mittal, Ying Yu Tai, Cheng Yuan Wu
Life of this patent
Estimating the term…
Abstract
An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.
Claims19
A method comprising:
- receiving a first instruction at a first sequencer in a first package with a first one or more memory components of a memory sub-system, the first instruction indicating a first sequence of memory access operations, wherein the first instruction is received from a controller of the memory sub-system that is coupled to the first sequencer and located outside the first package, and wherein the first one or more memory components have a first memory type;
- receiving a second instruction at a second sequencer in a second package with a second one or more memory components of a memory sub-system, the second instruction indicating a second sequence of memory access operations, wherein the second instruction is received from the controller of the memory sub-system that is coupled to the second sequencer and located outside the second package, wherein the second one or more memory components have a second memory type, and wherein the first memory type is different than the second memory type;
- performing, by a first processing device of the first sequencer, a first sequencing operation based on the first instruction to be performed on at least one of the first one or more memory components in the first package, wherein performing the first sequencing operation comprises reordering the first sequence of memory access operations based on rules related to data coherency;
- and
- performing, by a second processing device of the second sequencer, a second sequencing operation based on the second instruction to be performed on at least one of the second one or more memory components in the second package, wherein performing the second sequencing operation comprises reordering the second sequence of memory access operations based on rules related to data coherency.
2 more elements
A system comprising:
- one or more memory components;
- and
- a plurality of sequencer components, wherein each sequencer of the plurality of sequencers performs memory sequencing operations on memory components having a different memory type, wherein a first sequencer component of the plurality of sequencer components is in a first package comprising a subset of the one or more memory components having a first memory type, and wherein the first sequencer component is operatively coupled to a controller that is located outside the first package, the first sequencer component to:
- receive an instruction from the controller to perform a sequence of memory access operations;
- and
- perform a sequencing operation based on the instruction on at least one of the subset of the one or more memory components in the first package, wherein performing the sequencing operation comprises reordering the sequence of memory access operations based on rules related to data coherency.
3 more elements
A system comprising:
- a memory component;
- and
- a sequencer component, operatively coupled with the memory component, wherein the sequencer component is in a package comprising the memory component, and wherein the sequencer component is configured to interface with the memory component based on a memory type of the memory component, to:
- receive, from a controller that is external to the system, an instruction to perform a sequence of memory access operations;
- determine a sequencing operation to perform on the memory component based on the instruction;
- and
- perform the sequencing operation on the memory component, wherein performing the sequencing operation comprises reordering the sequence of memory access operations based on rules related to data coherency.
4 more elements
Dependencies are inferred from the claim text.