Ring structure of priority queues for memory cache

A computing device comprising:

• a processor comprising a plurality of processing engines;
• and
• a machine-readable storage storing instructions, the instructions executable by the processor to:
• store identifiers of a first set of cached data blocks in a ring structure comprising a plurality of queues, wherein each queue is associated with a different priority level, wherein the plurality of queues includes a subset of queues associated with an insertion range of priority levels;
• perform a plurality of partial rotations of the ring structure, wherein each partial rotation shifts the base pointer to a next higher queue;
• during the plurality of partial rotations of the ring structure, insert new identifiers of data blocks associated with a plurality of processing engines into the subset of queues;
• and
• maintain, for multiple partial rotations, an association between a first processing engine and a first queue of the subset of queues until the first queue exits the insertion range of priority levels.

A non-transitory machine-readable medium storing instructions that upon execution cause a processor to:

• store identifiers of a first set of data blocks in a ring structure comprising a plurality of queues, wherein each queue is associated with a different priority level;
• for each access of a first data block, increase a heat level associated with the first data block without moving an identifier of the first data block to a higher priority queue;
• and
• move only identifiers of data blocks in a lowest priority queue with heat values above a threshold to a set of queues associated with a predefined range of priority levels.